In Situ Studies of III-V Surfaces and High-K Atomic Layer Deposition

Atomic layer deposition (ALD) of high dielectric constant (high-k) materials for ULSI technologies is now widely adopted in Si-based CMOS production. Extending the scaling of integrated circuit technology has now resulted in the investigation of transistors incorporating alternative channel materials, such as III-V compounds. The control of the interfacial chemistry between a high-k dielectric and III-V materials presents a formidable challenge compared to that surmounted by Si-based technologies. The bonding configuration is obviously more complicated for a compound semiconductor, and thus an enhanced propensity to form interfacial defects is anticipated, as well as the need for surface passivation methods to mitigate such defects. In this work, we outline our recent results using in-situ methods to study the ALD high-k/III-V interface. We begin by briefly summarizing our results for III-As compounds, and then further discuss recent work on III-P and III-Sb compounds. While arsenides are under consideration for nMOS devices, antimonides are of interest for pMOS. InP is under consideration for quantum well channel MOS structures in order to serve as a better nMOS channel interface. In all cases, a high-k dielectric interface is employed to limit off-state tunneling current leakage.