scholarly journals How to Control Errors in Analog-To-Digital Conversion

1993 ◽  
Vol 7 (4) ◽  
pp. 408 ◽  
Author(s):  
James R. Matey ◽  
M.J. Lauterbach
Keyword(s):  
Digital Conversion ◽  
Analog To Digital ◽  
Analog To Digital Conversion

Energy Harvesting via Analog-to-Digital Conversion

2021 ◽  
Author(s):  
Neha Jain ◽  
Nir Shlezinger ◽  
Yonina C. Eldar ◽  
Anubha Gupta ◽  
Vivek Ashok Bohara
Keyword(s):  
Energy Harvesting ◽  
Digital Conversion ◽  
Analog To Digital ◽  
Analog To Digital Conversion

Design of a 20-Gsps 12-bit time-interleaved analog-to-digital conversion system

2021 ◽  
Vol 32 (3) ◽  
Author(s):  
Ruo-Shi Dong ◽  
Lei Zhao ◽  
Jia-Jun Qin ◽  
Wen-Tao Zhong ◽  
Yi-Chun Fan ◽  
...  
Keyword(s):  
Digital Conversion ◽  
Analog To Digital ◽  
Analog To Digital Conversion ◽  
Conversion System ◽  
Time Interleaved

1550 nm mode-locked semiconductor lasers for all-optical analog-to-digital conversion

2017 ◽  
Author(s):  
Evgenii S. Kolodeznyi ◽  
Innokenty I. Novikov ◽  
Andrey V. Babichev ◽  
Alexander S. Kurochkin ◽  
Andrey G. Gladyshev ◽  
...  
Keyword(s):  
Semiconductor Lasers ◽  
Digital Conversion ◽  
Analog To Digital ◽  
Analog To Digital Conversion ◽  
All Optical ◽  
Optical Analog

scholarly journals Photonic analog-to-digital conversion based on time-to-frequency mapping

2021 ◽  
pp. 127440
Author(s):  
Hao Chi ◽  
Qiulin Zhang ◽  
Shuna Yang ◽  
Bo Yang ◽  
Yanrong Zhai ◽  
...  
Keyword(s):  
Digital Conversion ◽  
Analog To Digital ◽  
Analog To Digital Conversion

SELF-TIMED ARCHITECTURE FOR MASKED SUCCESSIVE APPROXIMATION ANALOG-TO-DIGITAL CONVERSION

2007 ◽  
Vol 16 (01) ◽  
pp. 1-14
Author(s):  
TASKIN KOCAK ◽  
GEORGE R. HARRIS ◽  
RONALD F. DEMARA
Keyword(s):  
Successive Approximation ◽  
Cmos Technology ◽  
Digital Systems ◽  
Digital Converter ◽  
Digital Conversion ◽  
Analog To Digital ◽  
Analog Signals ◽  
Analog To Digital Conversion ◽  
Null Convention Logic ◽  
The One

In this paper, a novel architecture for self-timed analog-to-digital conversion is presented and designed using the NULL Convention Logic (NCL) paradigm. This analog-to-digital converter (ADC) employs successive approximation and a one-hot encoded masking technique to digitize analog signals. The architecture scales readily to any given resolution by utilizing the one-hot encoded scheme to permit identical logical components for each bit of resolution. The four-bit configuration of the proposed design has been implemented and assessed via simulation in 0.18-μm CMOS technology. Furthermore, the ADC may be interfaced with either synchronous or four-phase asynchronous digital systems.

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