SELF-TIMED ARCHITECTURE FOR MASKED SUCCESSIVE APPROXIMATION ANALOG-TO-DIGITAL CONVERSION

2007 ◽  
Vol 16 (01) ◽  
pp. 1-14
Author(s):  
TASKIN KOCAK ◽  
GEORGE R. HARRIS ◽  
RONALD F. DEMARA
Keyword(s):  
Successive Approximation ◽  
Cmos Technology ◽  
Digital Systems ◽  
Digital Converter ◽  
Digital Conversion ◽  
Analog To Digital ◽  
Analog Signals ◽  
Analog To Digital Conversion ◽  
Null Convention Logic ◽  
The One

In this paper, a novel architecture for self-timed analog-to-digital conversion is presented and designed using the NULL Convention Logic (NCL) paradigm. This analog-to-digital converter (ADC) employs successive approximation and a one-hot encoded masking technique to digitize analog signals. The architecture scales readily to any given resolution by utilizing the one-hot encoded scheme to permit identical logical components for each bit of resolution. The four-bit configuration of the proposed design has been implemented and assessed via simulation in 0.18-μm CMOS technology. Furthermore, the ADC may be interfaced with either synchronous or four-phase asynchronous digital systems.

scholarly journals Systematization and Comparison of the Binary Successive Approximation Variants

Sensors ◽  
2021 ◽  
Vol 21 (24) ◽  
pp. 8267
Author(s):  
Konrad Jurasz ◽  
Dariusz Kościelnik ◽  
Jakub Szyduczyński ◽  
Marek Miśkowicz
Keyword(s):  
Energy Consumption ◽  
Successive Approximation ◽  
Direct Conversion ◽  
Conversion Process ◽  
Digital Converter ◽  
Time Intervals ◽  
Digital Conversion ◽  
Analog To Digital ◽  
Analog To Digital Conversion ◽  
Physical Quantities

This paper presents a systematization and a comparison of the binary successive approximation (SA) variants. Three different variants are distinguished and all of them are applied in the analog-to-digital conversion. Regardless of an analog-to-digital converter circuit solution, the adoption of the specific SA variant imposes a particular character of the conversion process and related parameters. One of them is the ability to direct conversion of non-removeable physical quantities such as time intervals. Referencing to this aspect a general systematization of the variants and a name for each of them is proposed. In addition, the article raises the issues related to the complexity of implementation and energy consumption for each of the discussed binary SA variants. 

SSDCα – Inherently robust integrated biomimetic sensor-to-spike-to-digital converter based on peripheral neural ensembles

2016 ◽  
Vol 83 (9) ◽  
Author(s):  
Abhaya Chandra Kammara S. ◽  
Andreas König
Keyword(s):  
Digital Converter ◽  
Digital Conversion ◽  
Analog To Digital ◽  
Neural Ensembles ◽  
Analog To Digital Conversion ◽  
Technology Nodes ◽  
Biomimetic Sensor

AbstractRethinking analog to digital conversion has become extremely crucial in the race towards aggressively scaled technology nodes with decaying signal swings. The concept of more recent TDCs, which are completely designed in digital domain, make them simpler, easier to manufacture and faster to market. In previous work, LUCOS

A RE-CONFIGURABLE ARCHITECTURE FOR SWITCHED CAPACITOR SIGMA-DELTA ANALOG-TO-DIGITAL CONVERSION

2013 ◽  
Vol 22 (09) ◽  
pp. 1340012
Author(s):  
KAREN WAN ◽  
GIGI CHAN ◽  
WILLIAM WONG ◽  
KAM CHUEN WAN ◽  
BRYCE YAU ◽  
...  
Keyword(s):  
Fourth Order ◽  
Cmos Technology ◽  
Second Order ◽  
Switched Capacitor ◽  
Noise Shaping ◽  
Digital Conversion ◽  
Sigma Delta Modulator ◽  
Sigma Delta ◽  
Analog To Digital ◽  
Analog To Digital Conversion

A re-configurable switched capacitor sigma-delta analog-to-digital conversion architecture1,2 is proposed. The architecture consists of a MASH sigma delta modulator with nth lower-order (first- or second-order) loops cascaded together. Each loop can be powered on or off operating in high or low performance mode, according to application needs. The architecture can be configured to optimize performance and power consumption for specific resolution and applications. The architecture is proven by means of a prototype, implemented as a fourth-order and fabricated in a standard 0.18 um CMOS technology. The outputs of both high performance mode (fourth-order) and medium performance mode (second-order, first loop ON) are measured to demonstrate the configurability. The FFT demonstrates that the noise shaping for the fourth-order modulator is better than that of the second-order modulator with steeper noise shaping slope.

scholarly journals Design of 12-Bit SAR ADC using Split Capacitor Based DAC Architecture at 45nm CMOS Technology

2019 ◽  
Vol 8 (12) ◽  
pp. 2530-2535
Keyword(s):  
Successive Approximation ◽  
Medical Application ◽  
Cmos Technology ◽  
Sar Adc ◽  
Performance Parameters ◽  
Digital Converter ◽  
Analog To Digital ◽  
Common Mode Voltage ◽  
Split Capacitor ◽  
Increasing Demand

Nowadays, there is an increasing demand for Successive Approximation Register (SAR) based Analog to Digital Converter (ADC) in long battery applications like medical application, Sensors and many more. In this paper DAC circuit is designed using multiple capacitor and Multiple MUX for switching. A split based capacitor is used for boosting the speed of the architecture. In split based DAC no common mode voltage required and dynamic offset can be removed as well. In this work, 12-Bit DAC and encoder is designed using 2 Transistor MUX and 18 Transistor Full adders (12B-2TM-18TFA). 2T and 18T is used to design the MUX and FA. This entire architecture is implemented in Cadence Virtuoso 45nm CMOS technology. Simultaneously, 10B-12TM-36TFA architecture also implemented in this paper. The performance parameters like area, power, and delay, current is evaluated for both architectures. Result showed that 12B-2TM-18TFA architecture consumed less area, less power, less delay, and less current compared to 10B-12TM-36TFA.

Programmable Nonlinear Adc: An Illustrative Example

1996 ◽  
Vol 33 (3) ◽  
pp. 216-224
Author(s):  
Dinesh K. Anvekar ◽  
B. S. Sonde
Keyword(s):  
Transfer Characteristic ◽  
Analog To Digital Converter ◽  
Analytical Evaluation ◽  
Digital Converter ◽  
Digital Conversion ◽  
Analog To Digital ◽  
Analog To Digital Conversion ◽  
Experimental Implementation ◽  
Nonlinear Analog

Programmable nonlinear ADC: an illustrative example Programmable nonlinear analog-to-digital conversion is a new topic in EE curricula. With a view to introducing the EE student to the concept of transfer characteristic programmability of an analog-to-digital converter (ADC), a memory-prefetch programmable nonlinear ADC is presented. The design, analytical evaluation, and experimental implementation for the ADC are described.

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