A reconfigurable two-stage cyclic ADC for low-power applications in 3.3 V 0.35 µm CMOS

2016 ◽  
Vol 103 (12) ◽  
pp. 1998-2012 ◽  
Author(s):  
José Angel Díaz-Madrid ◽  
Ginés Doménech-Asensi ◽  
Matthias Oberst
Keyword(s):  
2011 ◽  
Vol 32 (2) ◽  
pp. 025008 ◽  
Author(s):  
Hongliang Zhao ◽  
Yiqiang Zhao ◽  
Junfeng Geng ◽  
Peng Li ◽  
Zhisheng Zhang

2008 ◽  
Vol E91-C (6) ◽  
pp. 894-902
Author(s):  
T. SATO ◽  
I. MATSUMOTO ◽  
S. TAKAGI ◽  
N. FUJII
Keyword(s):  

2011 ◽  
Vol 20 (01) ◽  
pp. 57-70 ◽  
Author(s):  
HONGLIANG ZHAO ◽  
YIQIANG ZHAO ◽  
PENG LI ◽  
JUNWEI JIANG ◽  
ZHISHENG ZHANG

A 12-bit cyclic analog to digital converter (ADC) used in long line array infrared sensors readout circuit is presented. The architecture of a low-power amplifier shared with two groups of switched capacitors is used to reduce power consumption. By adding cross-connected switches, the amplifier's offset is effectively canceled out. The improved redundant signed digit (RSD) correction technique is employed to compensate for the error resulting from the comparator's offset in sub-ADC, and the correction technique can tolerate high level of switched capacitor mismatch error, as well. The converter manufactured with Chartered 0.35 μm CMOS process exhibits 0.92 LSB maximum differential nonlinearity (DNL) and 1.5 LSB maximum integral nonlinearity (INL). The ADC has a 69.3 dB signal to noise and distortion ratio (SNDR) at 250 kS/s sample rate and 3 MHz clock frequency. It dissipates 0.8 mW with 3.3 V supply and occupies 0.22 × 0.9 mm2.


2016 ◽  
Vol 88 (2) ◽  
pp. 245-254 ◽  
Author(s):  
Gerardo Molina Salgado ◽  
Gordana Jovanovic Dolecek ◽  
Jose M. de la Rosa
Keyword(s):  

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