An evolutionary approach based design automation of low power CMOS Two-Stage Comparator and Folded Cascode OTA

2016 ◽  
Vol 70 (4) ◽  
pp. 398-408 ◽  
Author(s):  
K.B. Maji ◽  
R. Kar ◽  
D. Mandal ◽  
S.P. Ghoshal
Keyword(s):  
Low Power ◽  
Design Automation ◽  
Evolutionary Approach ◽  
Two Stage ◽  
Low Power Cmos ◽  
Folded Cascode

Enhancing transconductance of ultra‐low‐power two‐stage folded cascode OTA

2014 ◽  
Vol 50 (21) ◽  
pp. 1514-1516 ◽  
Author(s):  
M. Akbari ◽  
O. Hashemipour
Keyword(s):  
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Two Stage ◽  
Ultra Low Power ◽  
Folded Cascode

Evolutionary Approach of Adiabatic Logic Design on Low Power Solution �A Robust Survey

2012 ◽  
Vol 1 (2) ◽  
pp. 36-49
Author(s):  
A. Kishore Kumar ◽  
D. Somasundareswari ◽  
V. Duraisamy ◽  
T. Shunbaga Pradeepa
Keyword(s):  
Low Power ◽  
Evolutionary Approach ◽  
Logic Design ◽  
Adiabatic Logic

PVT ‐compensated low‐voltage and low‐power CMOS LNA for IoT applications

2020 ◽  
Vol 30 (11) ◽  
Author(s):  
Sajad Nejadhasan ◽  
Fatemeh Zaheri ◽  
Ebrahim Abiri ◽  
Mohammad Reza Salehi
Keyword(s):  
Low Power ◽  
Low Voltage ◽  
Iot Applications ◽  
Low Power Cmos ◽  
Cmos Lna
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