A low-power 10-bit 250-KSPS cyclic ADC with offset and mismatch correction

2011 ◽  
Vol 32 (2) ◽  
pp. 025008 ◽  
Author(s):  
Hongliang Zhao ◽  
Yiqiang Zhao ◽  
Junfeng Geng ◽  
Peng Li ◽  
Zhisheng Zhang
Keyword(s):  
Low Power ◽  
Mismatch Correction ◽  
Cyclic Adc

A LOW-POWER 12-BIT 250 KS/S CYCLIC ADC FOR LONG LINE ARRAY INFRARED SENSORS READOUT CIRCUIT

2011 ◽  
Vol 20 (01) ◽  
pp. 57-70 ◽  
Author(s):  
HONGLIANG ZHAO ◽  
YIQIANG ZHAO ◽  
PENG LI ◽  
JUNWEI JIANG ◽  
ZHISHENG ZHANG
Keyword(s):  
Low Power ◽  
Cmos Process ◽  
Readout Circuit ◽  
Clock Frequency ◽  
Infrared Sensors ◽  
Differential Nonlinearity ◽  
Line Array ◽  
Long Line ◽  
Correction Technique ◽  
Cyclic Adc

A 12-bit cyclic analog to digital converter (ADC) used in long line array infrared sensors readout circuit is presented. The architecture of a low-power amplifier shared with two groups of switched capacitors is used to reduce power consumption. By adding cross-connected switches, the amplifier's offset is effectively canceled out. The improved redundant signed digit (RSD) correction technique is employed to compensate for the error resulting from the comparator's offset in sub-ADC, and the correction technique can tolerate high level of switched capacitor mismatch error, as well. The converter manufactured with Chartered 0.35 μm CMOS process exhibits 0.92 LSB maximum differential nonlinearity (DNL) and 1.5 LSB maximum integral nonlinearity (INL). The ADC has a 69.3 dB signal to noise and distortion ratio (SNDR) at 250 kS/s sample rate and 3 MHz clock frequency. It dissipates 0.8 mW with 3.3 V supply and occupies 0.22 × 0.9 mm2.

scholarly journals Low power 9-bit 500 kS/s 2-stage cyclic ADC using OTA variable bias current

2020 ◽  
Vol 105 (1) ◽  
pp. 45-55
Author(s):  
José Ángel Díaz-Madrid ◽  
Ginés Doménech-Asensi ◽  
Ramón Ruiz-Merino ◽  
Juan Zapata ◽  
José Javier Martínez
Keyword(s):  
Low Power ◽  
Bias Current ◽  
Variable Bias ◽  
Cyclic Adc

Low-Power and Wide-Bandwidth Cyclic ADC With Capacitor and Opamp Reuse Techniques for CMOS Image Sensor Application

2009 ◽  
Vol 9 (12) ◽  
pp. 2044-2054 ◽  
Author(s):  
Jin-Fu Lin ◽  
Soon-Jyh Chang ◽  
Chin-Fong Chiu ◽  
Hann-Huei Tsai ◽  
Jiann-Jong Wang
Keyword(s):  
Low Power ◽  
Cmos Image Sensor ◽  
Image Sensor ◽  
Wide Bandwidth ◽  
Sensor Application ◽  
Cyclic Adc

A reconfigurable two-stage cyclic ADC for low-power applications in 3.3 V 0.35 µm CMOS

2016 ◽  
Vol 103 (12) ◽  
pp. 1998-2012 ◽  
Author(s):  
José Angel Díaz-Madrid ◽  
Ginés Doménech-Asensi ◽  
Matthias Oberst
Keyword(s):  
Low Power ◽  
Two Stage ◽  
Cyclic Adc

A low-power 14-bit hybrid incremental sigma-delta/cyclic ADC for X-ray sensor array

2016 ◽  
Author(s):  
Zhuo Zhang ◽  
Yacong Zhang ◽  
Miaomiao Fair ◽  
Meng Zhao ◽  
Dahe Liu ◽  
...  
Keyword(s):  
Low Power ◽  
Sensor Array ◽  
Sigma Delta ◽  
X Ray ◽  
Cyclic Adc
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