Suppression of photo-leakage current in amorphous silicon thin-film transistors by n-doped nanocrystalline silicon

2011 ◽  
Vol 44 (47) ◽  
pp. 475401 ◽  
Author(s):  
Hung-Chien Lin ◽  
King-Yuan Ho ◽  
Chih-Chieh Hsu ◽  
Jing-Yi Yan ◽  
Jia-Chong Ho
2004 ◽  
Vol 814 ◽  
Author(s):  
Alex Kattamis ◽  
I-Chun Cheng ◽  
Steve Allen ◽  
Sigurd Wagner

AbstractNanocrystalline silicon is a candidate material for fabricating thin film transistors with high carrier mobilities on plastic substrates. A major issue in the processing of nanocrystalline silicon thin film transistors (nc-Si:H TFTs) at ultralow temperatures is the quality of the SiO2gate dielectric. SiO2deposited at less than 250°C by radio frequency plasma enhanced chemical vapor deposition (rf-PECVD), and not annealed at high temperature after deposition, exhibits high leakage current and voltage shifts when incorporated into TFT's. Secondary ion mass spectrometry (SIMS) measurements show that the hydrogen concentration (NH) in PECVD oxide deposited at 150°C on crystalline silicon (x-Si) is ∼ 0.8 at. %. This is much higher than in thermal oxides on x-Si, which display concentrations of less than 0.003 at. %. The leakage current density for thermal oxides on x-Si at a bias of 10 V is ∼9×10−6A/cm2whereas for 200°C PECVD oxides on nc-Si:H the current is ∼1×10−4A/cm2. As the temperature of the SiO2deposition is reduced to 150°C the current density rises by up to two orders of magnitude more. The H which is suspected to cause the leakage current across the PECVD oxide originates from the nc-Si:H substrate and the SiH4source gas. We analyzed the 300-nm gate oxide in capacitor structures of Al / SiO2/n+nc-Si:H / Cr / glass, Al / SiO2/ n+nc-Si:H / x-Si, and Al / SiO2/ x-Si. Vacuum annealing the nc-Si:H prior to PECVD of the oxide drives H out of the nc-Si:H film and reduces the amount of H incorporated into the oxide that is deposited on top. SiO2film deposition from SiH4and N2O at high He dilution has a still greater effect on lowering NH. The leakage current at a 10 V bias dropped from ∼1×10−4A/cm2to about ∼2×10−6A/cm2using He dilution at 250°C, and the vacuum anneal of the nc-Si:H lowered it by an additional factor of two. Thus we observe that both the nc-Si:H anneal and the SiO2deposition at high He dilution lessen the gate leakage current.


2007 ◽  
Vol 54 (5) ◽  
pp. 1076-1082 ◽  
Author(s):  
Argyrios T. Hatzopoulos ◽  
Nikolaos Arpatzanis ◽  
Dimitrios H. Tassis ◽  
Charalabos A. Dimitriadis ◽  
Maher Oudwan ◽  
...  

2002 ◽  
Vol 715 ◽  
Author(s):  
H. Gleskova ◽  
S. Wagner ◽  
W. Soboyejo ◽  
Z. Suo

AbstractWe evaluated a-Si:H TFTs fabricated on polyimide foil under uniaxial compressive or tensile strain. The strain was induced by bending or stretching. All experiments confirmed that the on-current and hence the electron linear mobility depend on strain å as μ = μ0 (1 + 26·ε), where tensile strain has a positive sign. Upon the application of stress the mobility changes instantly and then remains unchanged in measurements up to 40 hours. In the majority of the TFTs the off-current and leakage current do not change. In tension, the TFTs fail mechanically at a strain of ∼ 3x10-2 but recover if the strain is released ‘immediately’.


1999 ◽  
Vol 38 (Part 1, No. 11) ◽  
pp. 6202-6206 ◽  
Author(s):  
Yoshimi Yamaji ◽  
Mitsushi Ikeda ◽  
Masahiko Akiyama ◽  
Takahiko Endo

2008 ◽  
Vol 92 (8) ◽  
pp. 083509 ◽  
Author(s):  
Hyun Jung Lee ◽  
Andrei Sazonov ◽  
Arokia Nathan

1992 ◽  
Vol 258 ◽  
Author(s):  
T. Globus ◽  
M. Shur ◽  
M. Hack

ABSTRACTOur experimental studies confirm that changes in a-Si Thin Film Transistors (TFTs) under voltage stress occur in the device channel and not in the contacts. We demonstrate that stressing an a-Si TFT not only shifts the device threshold voltage but can also changes the slope of the semilog subthreshold current dependence on the gate voltage. In addition, stressing can decrease the minimum leakage current. The creation of new localized states in the amorphous silicon under voltage stress qualitatively explains all these effects, while carrier tunneling and trapping in the gate insulator layer cannot by itself explain our data. At large negative gate voltages, the leakage current increases due to the holes injected into the channel. This hole current is also affected by voltage stress as can be predicted by the state creation mechanism.


2007 ◽  
Vol 28 (9) ◽  
pp. 803-805 ◽  
Author(s):  
A.T. Hatzopoulos ◽  
N.. Arpatzanis ◽  
D.H. Tassis ◽  
C.A. Dimitriadis ◽  
F.. Templier ◽  
...  

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