A process-independent, 800-MB/s, DRAM byte-wide interface featuring command interleaving and concurrent memory operation
1998 ◽
Vol 33
(11)
◽
pp. 1741-1751
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Keyword(s):
2004 ◽
Vol 19
(4)
◽
pp. 1175-1180
◽
2009 ◽
Vol 1
(4)
◽
pp. 58-67
◽
Keyword(s):