Characterization of oxide trap and interface trap creation during hot-carrier stressing of n-MOS transistors using the floating-gate technique

In sub-micrometre LDD NMOSFETs we were able to correlate an evolution of hot-carrier-induced gate currents obtained from floating-gate measurements with corresponding evolution of saturation transconductances. With this correlation, additional substrate current measurements, and the help of a 2D device simulation framework, we find that negative oxide-trapped charges of magnitude 2.5 × 1018 cm−3 are responsible for the experimental observations. This damage is located in the oxide at the edge of the gate over 100 Å (1 Å = 10−10 m) above the oxide–silicon interface, which is deep into the LDD structure and difficult to probe with the existing methods. Then we demonstrate how the in-channel interface states density can be profiled using a lateral-profiling charge-pumping technique. The coupling of the techniques mentioned above leads to the characterization of the entire oxide–silicon interface along the length of the gate. This is essential for the proper understanding of the directions for process improvements and the mechanisms of defect generation.

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Comments on "The generation and characterization of electron and hole traps created by hole injection during low gate voltage hot-carrier stressing of n-MOS transistors" [with reply]

IEEE Transactions on Electron Devices ◽

10.1109/16.121710 ◽

1992 ◽

Vol 39 (2) ◽

pp. 458-464 ◽

Cited By ~ 23

Author(s):

P. Heremans ◽

R. Bellens ◽

G. Groeseneken ◽

H.E. Maes

Keyword(s):

Gate Voltage ◽

Hole Injection ◽

Mos Transistors ◽

Hot Carrier ◽

Electron And Hole Traps

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Hydrogen/Deuterium Interaction With CMOS Transistor Device Structure: Sintering Process Studied by Sims

MRS Proceedings ◽

10.1557/proc-513-325 ◽

1998 ◽

Vol 513 ◽

Cited By ~ 5

Author(s):

P. J. Chen ◽

R. M. Wallace

Keyword(s):

Interfacial Region ◽

Sintering Process ◽

Dangling Bond ◽

Mos Transistors ◽

Hot Carriers ◽

Device Structure ◽

Hot Carrier ◽

Cmos Transistor ◽

Hydrogen Deuterium

ABSTRACTPassivation of the SiO2-Si interface by hydrogen/deuterium in MOS transistors serve to ensure their operating reliability against channel hot carriers. Physical characterization of device sintering process in deuterated forming gas (10%D2:90%N2) is carried out by dynamic SIMS on planar CMOS gate stack structures, in conjunction with device hot carrier electrical testing. It is found that incorporation of deuterium in the doped poly-Si/SiO2/Si interfacial region readily occurs under typical post-metallization sintering conditions, demonstrating that transport of deuterium through CMOS gate is an effective pathway in an encapsulated device structure with silicon nitride sidewalls. The measured Si-D areal densities in the interfacial region depend on gate poly-Si doping type, but in both cases, appear to be sufficient to achieve complete interface Si dangling bond (˜1012 cm−2) passivation for the SiO2-Si system.

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