Mismatch and parasitic effects of bridge capacitors in successive-approximation-register analog-to-digital converter’s (SAR-ADC) split capacitor digital-to-analog conversion (DAC) cause a significant performance deterioration. This paper presents a nonlinearity analysis based on an analytical model, and a modified calibration method utilizing a pre-bias bridge capacitor is accordingly proposed. The proposed method, which uses three-segment split capacitor DAC structure, can effectively eliminate over-calibration error caused by conventional structure. To verify the technique, a 14-bit SAR-ADC has been designed in 0.35-[Formula: see text]m 2P4M CMOS process with the PIP capacitor, and the simulation results show the method can further improve ADC performance.
An 18.39 fJ/Conversion-Step 1-MS/s 12-bit SAR ADC with Non-Binary Multiple-LSB-Redundant and Non-Integer-and-Split-Capacitor DAC
