A 10-bit 50-MS/s SAR ADC with Split-Capacitor Array Using Unity-Gain Amplifiers Applied in FOG Systems

2021 ◽  
Author(s):  
Tzung-Je Lee ◽  
Meng-Jie Wu ◽  
Yi-Jen Chiu ◽  
Chua-Chin Wang
Keyword(s):  
Sar Adc ◽  
Capacitor Array ◽  
Unity Gain ◽  
Split Capacitor

scholarly journals Linearity Analysis on a Series-Split Capacitor Array for High-Speed SAR ADCs

VLSI Design ◽  
2010 ◽  
Vol 2010 ◽  
pp. 1-8 ◽  
Author(s):  
Yan Zhu ◽  
U-Fat Chio ◽  
He-Gong Wei ◽  
Sai-Weng Sin ◽  
Seng-Pan U ◽  
...  
Keyword(s):  
High Speed ◽  
Average Power ◽  
Sar Adc ◽  
Capacitor Array ◽  
Medium Resolution ◽  
Charge Recycling ◽  
Split Capacitor ◽  
Array Structure ◽  
Conversion Performance ◽  
Binary Weighted

A novel Capacitor array structure for Successive Approximation Register (SAR) ADC is proposed. This circuit efficiently utilizes charge recycling to achieve high-speed of operation and it can be applied to high-speed and low-to-medium-resolution SAR ADC. The parasitic effects and the static linearity performance, namely, the INL and DNL, of the proposed structure are theoretically analyzed and behavioral simulations are performed to demonstrate its effectiveness under those nonidealities. Simulation results show that to achieve the same conversion performance the proposed capacitor array structure can reduce the average power consumed from the reference ladder by 90% when compared to the binary-weighted splitting capacitor array structure.

A novel split capacitor array switching scheme with proportional coefficient for SAR ADC

2018 ◽  
Vol 98 (3) ◽  
pp. 597-605 ◽  
Author(s):  
Ruixue Ding ◽  
Shaopeng Dong ◽  
Shubin Liu ◽  
Depeng Sun ◽  
Zhangming Zhu
Keyword(s):  
Sar Adc ◽  
Switching Scheme ◽  
Capacitor Array ◽  
Split Capacitor

Study of Split Capacitor DAC Mismatch and Calibration in SAR-ADC

2016 ◽  
Vol 26 (01) ◽  
pp. 1750003
Author(s):  
Yun Zhang ◽  
Yiqiang Zhao ◽  
Peng Dai
Keyword(s):  
Calibration Method ◽  
Sar Adc ◽  
Calibration Error ◽  
Cmos Process ◽  
Analog To Digital ◽  
Significant Performance ◽  
Performance Deterioration ◽  
Conventional Structure ◽  
Split Capacitor ◽  
Simulation Results

Mismatch and parasitic effects of bridge capacitors in successive-approximation-register analog-to-digital converter’s (SAR-ADC) split capacitor digital-to-analog conversion (DAC) cause a significant performance deterioration. This paper presents a nonlinearity analysis based on an analytical model, and a modified calibration method utilizing a pre-bias bridge capacitor is accordingly proposed. The proposed method, which uses three-segment split capacitor DAC structure, can effectively eliminate over-calibration error caused by conventional structure. To verify the technique, a 14-bit SAR-ADC has been designed in 0.35-[Formula: see text]m 2P4M CMOS process with the PIP capacitor, and the simulation results show the method can further improve ADC performance.

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