Voltage Followers for the Design of Sallen-Key Active Rc-Filters

In this paper consider the circuitry of voltage followers (VF) with unity-gain, intended for practical use in active Sallen-Key RC-filters (LPF, HPF, BPF, RF). The results of research and computer modeling of radiation-resistant and low-temperature VF in the LTSpice environment on models of CJFET transistors operating under the influence of neutron flux up to 10e14 n/cm2 and cryogenic temperatures up to -197°C are presented.

Influence of Modifications Related to Safe Operating Area Demands on Operation of a Specialized Medium/High-Voltage Unity-Gain Buffer

This paper presents safety-related modifications to the improved high-voltage unity-gain buffer and their impact on the operation quality of this circuit. The analyzed buffer architecture combines the virtues of source and gate followers. It provides high input impedance to the gate follower and voltage gain precision to the source follower while retaining a very simple structure and an extremely short signal path. These properties enable its various applications, e.g., as an interconnection of voltage and current mode function blocks in signal paths of medium- and high-voltage integrated circuits. The scrutinized buffer consists of MOS devices with different maximum interterminal voltages, which results in the necessity of enhancing its architecture with a set of safety devices to ensure non-destructive power-up, normal operation, and power-down phases of the buffer operation. The consequences of the implemented safety changes vs. the influence of the physical implementation process on the buffer operation capabilities are presented in comparison to its ancestral source and gate followers. The results show that the analyzed buffer retains the best signal processing quality among the compared buffer structures after the complete physical implementation process.

Nonlinear Analytical Model of Localized Sub-THz and THz Rectifications in FET Power Detectors

<div>A nonlinear analytical model for THz FET power detectors based on their distributed RC network is presented. This empirical model works well for both drain-unbiased and drain-biased THz FET responses. The physics-based analysis reveals that localized THz rectifications in long channel transistors may be mathematically expressed in the same way as regular RF frequency rectifications of a single lumped device. However, the one lumped FET model can’t work properly at THz frequencies without correct definitions of THz signals on its terminals and independently considers localized rectifications on the source and drain sides. An improved compact one lumped THz FET power detector model with additional Schottky diodes at the source and drain terminals is presented. THz FET detector can also perform a simultaneous self-amplification (active rectification) of the localized THz rectified dc signal when operates in the saturation regime beyond its unity gain frequency. A novel analytical expression for the localized THz dc rectified response is developed for FETs operating in the saturation regime. The presented physics-based model agrees excellently with the measured experimental results of GaAs HEMT transistors at 1.6THz under arbitrary biasing conditions. Many novel electronic designs can be implemented for Millimeter-wave and THz technologies based on the physical FET's nonlinear nature in this frequency range</div>

Nonlinear Analytical Model of Localized Sub-THz and THz Rectifications in FET Power Detectors

<div>A nonlinear analytical model for THz FET power detectors based on their distributed RC network is presented. This empirical model works well for both drain-unbiased and drain-biased THz FET responses. The physics-based analysis reveals that localized THz rectifications in long channel transistors may be mathematically expressed in the same way as regular RF frequency rectifications of a single lumped device. However, the one lumped FET model can’t work properly at THz frequencies without correct definitions of THz signals on its terminals and independently considers localized rectifications on the source and drain sides. An improved compact one lumped THz FET power detector model with additional Schottky diodes at the source and drain terminals is presented. THz FET detector can also perform a simultaneous self-amplification (active rectification) of the localized THz rectified dc signal when operates in the saturation regime beyond its unity gain frequency. A novel analytical expression for the localized THz dc rectified response is developed for FETs operating in the saturation regime. The presented physics-based model agrees excellently with the measured experimental results of GaAs HEMT transistors at 1.6THz under arbitrary biasing conditions. Many novel electronic designs can be implemented for Millimeter-wave and THz technologies based on the physical FET's nonlinear nature in this frequency range</div>

0.5 V CMOS Inverter-Based Transconductance Amplifier with Quiescent Current Control

A two-stage CMOS transconductance amplifier based on the inverter topology, suitable for very low supply voltages and exhibiting rail-to-rail output capability is presented. The solution consists of the cascade of a noninverting and an inverting stage, both characterized by having only two complementary transistors between the supply rails. The amplifier provides class-AB operation with quiescent current control obtained through an auxiliary loop that utilizes the MOSFETs body terminals. Simulation results, referring to a commercial 28 nm bulk technology, show that the quiescent current of the amplifier can be controlled quite effectively, even adopting a supply voltage as low as 0.5 V. The designed solution consumes around 500 nA of quiescent current in typical conditions and provides a DC gain of around 51 dB, with a unity gain frequency of 1 MHz and phase margin of 70 degrees, for a parallel load of 1 pF and 1.5 MΩ. Settling time at 1% is 6.6 μs, and white noise is 125 nV/Hz.

A QFGMOS-Based gm-Boosted and Adaptively Biased Two-Stage Amplifier Offering Very High Gain and High Bandwidth

A low voltage low power two-stage CMOS amplifier with high open-loop gain, high gain bandwidth product (GBW) and enhanced slew rate is presented in this work. The proposed circuit makes use of folded cascode gm-boosting cells in conjunction with a low voltage gain enhanced cascode mirror using quasi-floating gate (QFGMOS) transistors. QFGMOS transistors are also used in input pair and adaptive biasing, which facilitate large dynamic output current in the presented circuit. Consequently, the slew rate is enhanced without much increase in static power dissipation. The unity gain frequency (UGF) and dc gain of the circuit are 29.4[Formula: see text]MHz and 132[Formula: see text]dB, respectively. The amplifier is operated at 0.6[Formula: see text]V dual supply with 89[Formula: see text][Formula: see text]W power consumption and has a nearly symmetrical average slew rate of 51.5[Formula: see text]V/[Formula: see text]s. All simulations including Monte Carlo and corner analysis are carried out using 180-nm CMOS technology for validating the design with help of spice tools.

A Low-Power, High-Gain Amplifier with Rail-to-Rail Operating Capability: Applications to Biomedical Signal Processing

low-voltage, low-power, rail-to-rail, two-stage trans-conductance amplifier is presented. The structure exploits body-driven transistors, configured in folded-cascode structure. To reduce the power consumption, the transistors are biased in the subthreshold region. The Specter RF simulation results which are conducted in TSMC 180nm CMOS standard process proves the well-performance of the proposed structure. The performance of the proposed structure against process variations is checked through process corners and Monte Carlo simulations. The results prove the robustness of the proposed amplifier against process uncertainties. Some important specifications of the design derived from circuit simulations are 93.36 dB small-signal gain, 14.4 PV2/Hz input referred noise power, 26.5 kHz unity gain frequency, 20 V/ms slew rate. The proposed structure draws 260 nW power from 0.5 V power supply and is loaded with a 15 pF loading capacitor. The input common mode range of structure is from 0 to 0.5 V.

A Novel OTA Architecture Exploiting Current Gain Stages to Boost Bandwidth and Slew-Rate

A novel architecture and design approach which make it possible to boost the bandwidth and slewrate performance of operational transconductance amplifiers (OTAs) are proposed and employed to design a low-power OTA with top-of-class small-signal and large-signal figures of merit (FOMs). The proposed approach makes it possible to enhance the gain, bandwidth and slew-rate for a given power consumption and capacitive load, achieving more than an order of magnitude better performance than a comparable conventional folded cascode amplifier. Current mirrors with gain and a push–pull topology are exploited to achieve symmetrical sinking and sourcing output currents, and hence class-AB behavior. The resulting OTA was implemented using the 130 nm STMicroelectronics process, with a supply voltage of 1 V and a power consumption of only 1 µW. Simulations with a 200 pF load capacitance showed a gain of 92 dB, a unity-gain frequency of 141 kHz, and a peak slew-rate of 30 V/ms, with a phase margin of 80°, and good noise, PSRR and CMRR performance. The small-signal and large-signal current and power FOMs are the highest reported in the literature for comparable amplifiers. Extensive parametric and Monte Carlo simulations show that the OTA is robust against process, supply voltage and temperature (PVT) variations, as well as against mismatches.

Unity-Gain Zero-Offset CMOS Buffer with Improved Feedforward Path

A voltage unity-gain zero-offset CMOS amplifier with reduced gain error and increased PSRR (power supply rejection ratio) is proposed. The amplifier uses two feed mechanisms, negative feedback and supporting positive feedforward, to achieve low deviation from unit gain over the entire input range. The circuit, designed in a standard 180-nanometer 1.8-voltage CMOS process, is compared with two known buffers of similar topology, also designed in the same process. Simulations show that, with the same supply (1.8 V), power (1.2 mW), load (12 pF), bandwidth (50 MHz), and similar area (600 µm2), the proposed buffer achieves the lowest gain error (0.3%) and the highest PSRR (72 dB).