Hardware Implementation of CORDIC Algorithm

Author(s):  
Anuvab Sahoo ◽  
Mamata Panigrahy
2012 ◽  
Vol 588-589 ◽  
pp. 727-730
Author(s):  
Zong Yao Liu ◽  
Wei Hua Zhu ◽  
Zhen Hua Qu

For the shortcomings that computation speed of the DDS decreases with iterations increasing in CORDIC algorithm., the traditional algorithm of multiple iterations is displaced by a point of decompose predict the direction of rotation and multi-level iterative parallel computing method in this paper. The function simulation results show that the improved algorithm enhance the computation speed and maintain data high precision. This design has high computing speed, high precision and simple hardware implementation etc.


2014 ◽  
Vol 981 ◽  
pp. 82-85
Author(s):  
Bin Yu ◽  
Yang Guang

CORDIC Algorithm is widely applicable to the hardware implementation of DSP, and it attaches a great importance in many hardware implementations of DSP for a lot of arithmetic operations are simplified to simple addition operations and shifting operations. The FPGA implement of sine and cosine functions are achieved through CORDIC Algorithm in the paper, and the input and output data of the entire structure complies with IEEE754 standards. The basic theory of CORDIC Algorithm is introduced first in the paper, then the hardware iterative formula and the flow chart get out of basic formulas are given, and the structure of the design is introduced in detail, at last synthesis and simulation results are given.


Electronics ◽  
2021 ◽  
Vol 10 (20) ◽  
pp. 2533
Author(s):  
Wenjia Fu ◽  
Jincheng Xia ◽  
Xu Lin ◽  
Ming Liu ◽  
Mingjiang Wang

CORDIC algorithm is used for low-cost hardware implementation to calculate transcendental functions. This paper proposes a low-latency high-precision architecture for the computation of hyperbolic functions sinhx and coshx based on an improved CORDIC algorithm, that is, the QH-CORDIC. The principle, structure, and range of convergence of the QH-CORDIC are discussed, and the hardware circuit architecture of functions sinhx and coshx using the QH-CORDIC is plotted in this paper. The proposed architecture is implemented using an FPGA device, showing that it has 75% and 50% latency overhead over the two latest prior works. In the synthesis using TSMC 65 nm standard cell library, ASIC implementation results show that the proposed architecture is also superior to the two latest prior works in terms of total time (latency × period), ATP (area × total time), total energy (power × total time), energy efficiency (total energy/efficient bits), and area efficiency (efficient bits/area/total time). Comparison of related works indicates that it is much more favorable for the proposed architecture to perform high-precision floating-point computations on functions sinhx and coshx than the LUT method, stochastic computing, and other CORDIC algorithms.


Author(s):  
Alexey V. Sokolovskiy ◽  
Evgeny A. Veisov ◽  
Valery N. Tyapkin ◽  
Dmitry D. Dmitriev

The fixed-point hardware architecture of the QR decomposition is constrained by a several issues that leads to decrease of a compute accuracy depending on a matrix size. In this article described the hardware architectures based on CORDIC algorithm and approximation functions. As a basis technique is used a Givens rotation technique, because it is a most suitable technique for hardware implementation


2013 ◽  
Vol 380-384 ◽  
pp. 1812-1815
Author(s):  
Bin Yu ◽  
Yang Guang ◽  
Hai Huang

CORDIC Algorithm is widely applicable to the hardware implementation of DSP, and it attaches a great importance in many hardware implementations of DSP for a lot of arithmetic operations are simplified to simple addition operations and shifting operations. The FPGA implement of sine and cosine functions are achieved through CORDIC Algorithm in the paper, and the input and output data of the entire structure complies with IEEE754 standards. The basic theory of CORDIC Algorithm is introduced first in the paper, then the hardware iterative formula and the flow chart get out of basic formulas are given, and the structure of the design is introduced in detail, at last synthesis and simulation results are given.


ForScience ◽  
2020 ◽  
Vol 8 (1) ◽  
pp. e00685
Author(s):  
Ricardo Gonçalves de Aguiar ◽  
Valfride Wallace do Nascimento ◽  
Fernando Lessa de Oliveira Magalhães ◽  
Hugo Daniel Hernandez Herrera

O presente trabalho apresenta a implementação em hardware para cálculo das funções trigono-métricas seno e cosseno por meio de rotação vetorial utilizando o algoritmo CORDIC. O código foi sintetizado no FPGA DE10-Lite da Terasic Inc. com as ferramentas de desenvolvimento da Altera/Intel para família MAX 10.  Com o objetivo de avaliar o desempenho da implementação em hardware, é realizado uma comparação com o algoritmo desenvolvido em Python e seus resultados são apresentados.  Tais resultados demonstram a precisão numérica da arquitetura proposta para a implementação do CORDIC no FPGA versus Python, não considerando o  tempo de execução. Palavras-chave: CORDIC. Verilog. FPGA.   Implentation of Cordic algorithm for sine and cosine calculation in FPGA Abstract The present work presents the hardware implementation for calculating the trigonometric functions sine and cosine by means of vector rotation using the CORDIC algorithm. The code was synthetized in the DE10-Lite Board from Terasic Inc. with Altera/Intel development tools for MAX Family 10. In order to evaluate the performance of the hardware implementation, a comparison with the algorithm developed in Python is performed and its results are presented. These results demonstrate the numerical precision of the proposed architecture for the implementation of CORDIC in FPGA versus Python, not considering the execution time. Keywords: CORDIC. Verilog. FPGA. Python.


Author(s):  
Muhammad Nasir Ibrahim ◽  
Chen Kean Tack ◽  
Mariani Idroas ◽  
Siti Noormaya Bilmas ◽  
Zuraimi Yahya

Sign in / Sign up

Export Citation Format

Share Document