A Novel Multitask Scheduling and Distributed Collaborative Computing Method of Edge Nodes in the Internet of Things

In this paper, we propose a novel multitask scheduling and distributed collaborative computing method for quality of service (QoS) guaranteed delay-sensitive services in the Internet of Things (IoT). First, we propose a multilevel scheduling framework combining the process and thread scheduling for reducing the processing delay of multitype services of a single edge node in IoT, where a preemptive static priority process scheduling algorithm is adopted for different types of services and a dynamic priority-based thread scheduling algorithm is proposed for the same type of services with high concurrency. Furthermore, for reducing the processing delay of computation-intensive services, we propose a distributed task offloading algorithm based on a multiple 0-1 knapsack model with value limitation with the collaboration of multiple edge nodes to minimize the processing delay. Simulation results show that the proposed method can significantly reduce not only the scheduling delay of a large number of time-sensitive services in single edge node but also the process delay of computation-intensive service collaborated by multiple edge nodes.

Supply and Demand Matching of Financial Support Policies for Private Enterprises Based on Text Measurement

The degree of matching between supply and demand for financial support policies is a key factor for policy effectiveness. In this paper, we use policy text computing method that integrates topic mining, text classification, and training set predictions to study the supply and demand matching of China’s financial support policies for private enterprises. We find that supply and demand match for policies on diversified financing channels. However, there is mismatch in financial service facilitation policies and local subsidy policies. Our research implies that China’s development of a multiple-layer financial market has promoted the diversification of financing channels, which has improved the financing conditions for private enterprises. However, financial service network is still not convenient to facilitate private enterprises.

Task Offloading Strategy and Simulation Platform Construction in Multi-User Edge Computing Scenario

Various types of service applications increase the amount of computing in vehicular networks. The lack of computing resources of the vehicle itself will hinder the improvement of network performance. Mobile edge computing (MEC) technology is an effective computing method that is used to solve this problem at the edge of network for multiple mobile users. In this paper, we propose the multi-user task offloading strategy based on game theory to reduce the computational complexity and improve system performance. The task offloading decision making as a multi-user task offloading game is formulated to demonstrate how to achieve the Nash equilibrium (NE). Additionally, a task offloading algorithm is designed to achieve a NE, which represents an optimal or sub-optimal system overhead. In addition, the vehicular communication simulation frameworks Veins, SUMO model and OMNeT++ are adopted to run the proposed task offloading strategy. Numerical results show that the system overhead of the proposed task offloading strategy can degrade about 24.19% and 33.76%, respectively, in different scenarios.

Real-time Selective Harmonic Minimization using a Hybrid Analog/Digital Computing Method

We present a hybrid analog/digital computing circuit to solve a selective harmonic minimization problem. The approach leverages favorable attributes of digital and analog controllers to yield a fast and scalable optimization solver. A digital microcontroller programs the cost function and other user-defined inputs to the optimization. Voltages in the circuit represent switching angles in the optimization problem. In steady state, the voltages converge to Karush–Kuhn–Tucker (KKT) points of the problem. We present a specific realization of the computing circuit that solves for eight independent switching angles for a quarter-wave symmetric PWM driven two-level single-phase inverter. Seven undesired harmonics are minimized while retaining control over the modulation index. The proposed computing circuit is verified with simulations and a PCB hardware implementation. The experimental results demonstrate that the proposed circuit can converge to the optimal solution in less than 5.0 ms, which is substantially faster than existing methods and facilitates real-time implementation. Moreover, the steady-state power consumption of the PCB implementation is approximately 750 mW, which is also significantly lower than published methods for comparable applications. The computing circuit is utilized to generate the PWM for a 2 kW single-phase inverter, which validates its feasibility in practical applications.

Real-time Selective Harmonic Minimization using a Hybrid Analog/Digital Computing Method

We present a hybrid analog/digital computing circuit to solve a selective harmonic minimization problem. The approach leverages favorable attributes of digital and analog controllers to yield a fast and scalable optimization solver. A digital microcontroller programs the cost function and other user-defined inputs to the optimization. Voltages in the circuit represent switching angles in the optimization problem. In steady state, the voltages converge to Karush–Kuhn–Tucker (KKT) points of the problem. We present a specific realization of the computing circuit that solves for eight independent switching angles for a quarter-wave symmetric PWM driven two-level single-phase inverter. Seven undesired harmonics are minimized while retaining control over the modulation index. The proposed computing circuit is verified with simulations and a PCB hardware implementation. The experimental results demonstrate that the proposed circuit can converge to the optimal solution in less than 5.0 ms, which is substantially faster than existing methods and facilitates real-time implementation. Moreover, the steady-state power consumption of the PCB implementation is approximately 750 mW, which is also significantly lower than published methods for comparable applications. The computing circuit is utilized to generate the PWM for a 2 kW single-phase inverter, which validates its feasibility in practical applications.