A performance-oriented circuit partitioning algorithm with logic-block replication for multi-FPGA systems
Circuit partitioning algorithm for low-power design under area constraints using simulated annealing
1999 ◽
Vol 146
(1)
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pp. 8
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Keyword(s):
Keyword(s):
2020 ◽
Vol 19
(3)
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pp. 1232-1248
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