A Sequential Circuit Partitioning Algorithm for Dynamically Reconfigurable FPGAs

2007 International Conference on Communications, Circuits and Systems ◽

10.1109/icccas.2007.4348258 ◽

2007 ◽

Author(s):

Chi-Chou Kao ◽

Tzu-Chiang Tai ◽

Yun-Yi Hwang ◽

Yen-Tai Lai

Keyword(s):

Circuit Partitioning ◽

Sequential Circuit ◽

Dynamically Reconfigurable ◽

Partitioning Algorithm

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Circuit partitioning algorithm for low-power design under area constraints using simulated annealing

IEE Proceedings - Circuits Devices and Systems ◽

10.1049/ip-cds:19990276 ◽

1999 ◽

Vol 146 (1) ◽

pp. 8 ◽

Author(s):

I.-S. Choi ◽

S.-Y. Hwang

Keyword(s):

Simulated Annealing ◽

Low Power ◽

Low Power Design ◽

Circuit Partitioning ◽

Partitioning Algorithm

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An improved circuit-partitioning algorithm based on min-cut equivalence relation

Integration ◽

10.1016/s0167-9260(03)00032-4 ◽

2003 ◽

Vol 36 (1-2) ◽

pp. 55-68 ◽

Author(s):

Xianyang Jiang ◽

Xubang Shen ◽

Tianxu Zhang ◽

Huayu Liu

Keyword(s):

Equivalence Relation ◽

Circuit Partitioning ◽

Partitioning Algorithm ◽

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A HW/SW partitioning algorithm for dynamically reconfigurable architectures

Proceedings Design, Automation and Test in Europe. Conference and Exhibition 2001 ◽

10.1109/date.2001.915109 ◽

2002 ◽

Author(s):

J. Noguera ◽

R.M. Badia

Keyword(s):

Reconfigurable Architectures ◽

Dynamically Reconfigurable ◽

Partitioning Algorithm

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Application of adaptive circuit partitioning algorithm to reduction of interconnections length between elements of VLSI circuit

9th International Conference on Electronics, Circuits and Systems ◽

10.1109/icecs.2002.1046259 ◽

2003 ◽

Author(s):

W. Szczesniak

Keyword(s):

Vlsi Circuit ◽

Circuit Partitioning ◽

Partitioning Algorithm ◽

Adaptive Circuit

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A new architecture for time-multiplexed FPGA and its circuit partitioning algorithm

TENCON 2008 - 2008 IEEE Region 10 Conference ◽

10.1109/tencon.2008.4766674 ◽

2008 ◽

Author(s):

Yen-Tai Lai ◽

Tzu-Chiang Tai ◽

Chung-Wei Liu

Keyword(s):

Circuit Partitioning ◽

Partitioning Algorithm

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Circuit partitioning for dynamically reconfigurable FPGAs

Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field programmable gate arrays - FPGA '99 ◽

10.1145/296399.296456 ◽

1999 ◽

Author(s):

Huiqun Liu ◽

D. F. Wong

Keyword(s):

Circuit Partitioning ◽

Dynamically Reconfigurable

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Temporal Partitioning Algorithm for Dynamically Reconfigurable Computing Systems

Informatics Engineering and Information Science - Communications in Computer and Information Science ◽

10.1007/978-3-642-25327-0_38 ◽

2011 ◽

pp. 443-452

Author(s):

Ramzi Ayadi ◽

Bouaoui Ouni ◽

Abdellatif Mtibaa

Keyword(s):

Reconfigurable Computing ◽

Computing Systems ◽

Temporal Partitioning ◽

Dynamically Reconfigurable ◽

Partitioning Algorithm

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A circuit partitioning algorithm under path delay constraints

IEEE. APCCAS 1998. 1998 IEEE Asia-Pacific Conference on Circuits and Systems. Microelectronics and Integrating Systems. Proceedings (Cat. No.98EX242) ◽

10.1109/apccas.1998.743671 ◽

2002 ◽

Author(s):

J. Minami ◽

T. Koide ◽

S. Wakabayashi

Keyword(s):

Circuit Partitioning ◽

Delay Constraints ◽

Partitioning Algorithm

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Scheduling driven circuit partitioning algorithm for multiple FPGAs using time-multiplexed, off-chip, multi-casting interconnection architecture

Microprocessors and Microsystems ◽

10.1016/j.micpro.2004.03.004 ◽

2004 ◽

Vol 28 (5-6) ◽

pp. 341-350

Author(s):

Young-Su Kwon ◽

Chong-Min Kyung

Keyword(s):

Circuit Partitioning ◽

Partitioning Algorithm

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Multi-level sequential circuit partitioning for test vector generation for low power test in VLSI

International Journal of Engineering Science and Technology ◽

10.4314/ijest.v2i11.64556 ◽

2011 ◽

Vol 2 (11) ◽

Author(s):

VH Prathyush ◽

K Somasundaram

Keyword(s):

Low Power ◽

Test Vector ◽

Circuit Partitioning ◽

Sequential Circuit ◽

Low Power Test ◽

Vector Generation ◽

Multi Level ◽

Test Vector Generation

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