Analysis of a boost-type power factor corrector using a conductance model

Author(s):  
DaFeng Weng ◽  
S. Yuvarajan
2017 ◽  
Vol 32 (11) ◽  
pp. 8293-8311 ◽  
Author(s):  
Chung-pui Tung ◽  
Henry Shu-hung Chung ◽  
Ken Kuen-Faat Yuen

Energies ◽  
2020 ◽  
Vol 13 (20) ◽  
pp. 5523
Author(s):  
Rodrigo De A. Teixeira ◽  
Werbet L. A. Silva ◽  
Guilherme A. P. De C. A. Pessoa ◽  
Joao T. Carvalho Neto ◽  
Elmer R. L. Villarreal ◽  
...  

This paper analyzes a Digital Signal Processor (DSP) based One Cycle Control (OCC) strategy for a Power Factor Corrector (PFC) rectifier with Common-mode Voltage (CMV) immunity. It is proposed a strategy that utilizes an emulated-resistance-controller in closed-loop configuration to set the dc-link voltage to achieve unity power factor (UPF). It is shown that if the PFC can achieve UPF condition and if the phase voltage is only affected by CMV, then phase current is free from CMV, as well as a lead-lag compensator (LLC) to average phase current.


2021 ◽  
Vol 2 (2) ◽  
pp. 29-35
Author(s):  
Dmitry A. Sorokin ◽  
◽  
Sergey I. Volskiy ◽  
Jaroslav Dragoun ◽  
◽  
...  

The paper suggests a control system of a three-phase power factor corrector. The study of the control system operation is carried out and the expressions for calculating the permissible values of error amplifier factors are obtained. The influence of the error amplifier parameters on phase current quality is investigated. The dependence of total harmonic distortion input current on a combination of error amplifier parameters is obtained at a given value of power factor. The conditions under which the total harmonic distortion input current has the minimum value are found out. This article is of interest to power electronics engineers, who are aimed at developing a three-phase power factor corrector.


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