A Fully-Integrated 180 nm CMOS 1.2 V Low-Dropout Regulator for Low-Power Portable Applications

This paper presents the design and postlayout simulation results of a capacitor-less low dropout (LDO) regulator fully integrated in a low-cost standard 180 nm Complementary Metal-Oxide-Semiconductor (CMOS) technology which regulates the output voltage at 1.2 V from a 3.3 to 1.3 V battery over a –40 to 120°C temperature range. To meet with the constraints of system-on-chip (SoC) battery-operated devices, ultralow power (Iq = 8.6 µA) and minimum area consumption (0.109 mm2) are maintained, including a reference voltage Vref = 0.4 V. It uses a high-gain dynamically biased folded-based error amplifier topology optimized for low-voltage operation that achieves an enhanced regulation-fast transient performance trade-off.

Design and Simulation of a Capless Low Drop Out Voltage Regulator

Portable electronic devices mostly used battery as their primary source for operation hence longer running batteries or Power resources or vital for any portable device need for stable voltage supplies have led to the development of low dropout voltage regulators low dropout regulators provide stable regulated output voltage in various operating conditions which makes it useful in portable devices that design of high performance and stable low dropout voltage regulator is a challenge nowadays with decreasing device size and increasing power densities. The proposed circuit used a 5pack architecture of error amplifier. This paper proposes the study of behavior of the LDO voltage regulator with internal capacitors i.e., capless. The regulated voltage of 1.8V is obtained using the typical power supply of 2.2V obtained dropout voltage of 400mv with the delay of 12.77micro sec, power consumed 1.816W. The proposed design produced DC gain of 31.77db,with the load current variation of 0 to 20mA. The capless LDO architecture is verified in the Cadence 180nm technology. The architecture provides a stable gain and plot for both Temperature and Load Variations. The stability issues are overcome using the compensation techniques which uses a current amplifier and a capacitor in the differentiator configuration. The current amplifier implemented uses current mirror with current copying ratio of unity.

Design Techniques for Low-Power and Low-Voltage Bandgaps

Reverse bandgaps generate PVT-independent reference voltages by means of the sums of pairs of currents over individual matched resistors: one (CTAT) current is proportional to VEB; the other one (PTAT) is proportional to VT (Thermal voltage). Design guidelines and techniques for a CMOS low-power reverse bandgap reference are presented and discussed in this paper. The paper explains firstly how to design the components of the bandgap branches to minimize circuit current. Secondly, error amplifier topologies are studied in order to reveal the best one, depending on the operation conditions. Finally, a low-voltage bandgap in 65 nm CMOS with 5 ppm/°C, with a DC PSR of −91 dB, with power consumption of 5.2 μW and with an area of 0.0352 mm2 developed with these techniques is presented.

Design of a Novel Current Mode Charge Pump for Very-Low-Voltage Applications in 130 nm SOI-BCD Technology

A novel charge pump with current mode control suitable to work under a very-low-voltage supply is proposed in this paper. The proposed charge pump consists of two sections. The first section is a power switches stage which consists of seven cascaded DEPMOS power switches. The second section is a low voltage stage which consists of a Low Voltage Level Shifter, Current Mode control, Follower Amplifier, Error Amplifier, Soft Start Comparator, and Skip mode & Over Voltage Comparator. The charge pump has been designed, simulated, and layout in Cadence using TSMC 130 nm SOI technology with LDMOS transistors, which have very low on-resistance. The input range of the charge pump is 2.7– 4.4 V, and it can supply up to 100 mA load current. The maximum efficiency is 90%, and the chip area is only 0.597 mm².

Study of the Influence of Control System Parameters on the Quality of the Input Current of a Three-Phase Power Factor Corrector

The paper suggests a control system of a three-phase power factor corrector. The study of the control system operation is carried out and the expressions for calculating the permissible values of error amplifier factors are obtained. The influence of the error amplifier parameters on phase current quality is investigated. The dependence of total harmonic distortion input current on a combination of error amplifier parameters is obtained at a given value of power factor. The conditions under which the total harmonic distortion input current has the minimum value are found out. This article is of interest to power electronics engineers, who are aimed at developing a three-phase power factor corrector.

A VERY LOW-DROPOUT VOLTAGE REGULATOR IN 0.18-M CMOS TECHNOLOGY FOR POWER MANAGEMENT SYSTEM

This paper proposes the design of a very low-dropout (LDO) voltage regulator in 0.18-mm CMOS technology. The proposed LDO regulator consists of voltage reference, symmetrical operational transconductance amplifier (OTA), PMOS transistor, resistive feedback network and output capacitor. The NMOS symmetrical OTA is implemented as an error amplifier and a PMOS transistor is employed as a pass device to improve gain and minimize low dropout voltage, respectively. The proposed design is simulated using Spectre simulator in Cadence software to verify its regulator performance. The simulation results show that the proposed LDO is capable to operate from a supply voltage of 1.7-2.0 V with a low dropout voltage of 19.3 mV at a maximum 50 mA load current to regulate output voltage 1.5 V. The active chip is 2.96 mm2 in size. The performance of the proposed LDO is suitable to enhance power management for system on chip (SoC) applications.