Comparison between latency insertion method (LIM) and relaxation method in thermal integrity analysis

2015 Asia-Pacific Symposium on Electromagnetic Compatibility (APEMC) ◽

10.1109/apemc.2015.7175274 ◽

2015 ◽

Author(s):

Kazuki Sakamoto ◽

Tadatoshi Sekine ◽

Hideki Asai

Keyword(s):

Relaxation Method ◽

Insertion Method ◽

Latency Insertion ◽

Integrity Analysis ◽

Thermal Integrity

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A comparison between latency insertion method and relaxation method in transient thermal analysis

2016 Asia-Pacific International Symposium on Electromagnetic Compatibility (APEMC) ◽

10.1109/apemc.2016.7522997 ◽

2016 ◽

Author(s):

Anh Ha Ngo ◽

Tadatoshi Sekine ◽

Hideki Asai

Keyword(s):

Thermal Analysis ◽

Relaxation Method ◽

Transient Thermal Analysis ◽

Insertion Method ◽

Latency Insertion ◽

Transient Thermal

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Latency insertion method for the analysis of steady state on-chip power distribution networks and transient simulation of lossy interconnects

2008 Asia-Pacific Microwave Conference ◽

10.1109/apmc.2008.4958455 ◽

2008 ◽

Author(s):

D. Klokotov ◽

J. Schutt-Aine

Keyword(s):

Steady State ◽

Power Distribution ◽

Distribution Networks ◽

Transient Simulation ◽

Power Distribution Networks ◽

Insertion Method ◽

Latency Insertion ◽

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Multi-Rate Latency insertion Method for the Fast Transient Simulation of Large Networks with Nonlinear iermination

2006 IEEE Electrical Performane of Electronic Packaging ◽

10.1109/epep.2006.321211 ◽

2006 ◽

Author(s):

Noritake Tsuboi ◽

Hideki Asai

Keyword(s):

Transient Simulation ◽

Large Networks ◽

Insertion Method ◽

Latency Insertion ◽

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Voltage‐in‐current formulation for the latency insertion method for improved stability

Electronics Letters ◽

10.1049/el.2016.3223 ◽

2016 ◽

Vol 52 (23) ◽

pp. 1904-1906 ◽

Author(s):

K.H. Tan ◽

P. Goh ◽

M.F. Ain

Keyword(s):

Current Formulation ◽

Insertion Method ◽

Latency Insertion ◽

Improved Stability

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Improved latency insertion method for simulation of large networks with low latency

Electrical Performance of Electronic Packaging, ◽

10.1109/epep.2002.1057878 ◽

2003 ◽

Author(s):

R. Gao ◽

J.E. Schutt-Aine

Keyword(s):

Low Latency ◽

Large Networks ◽

Insertion Method ◽

Latency Insertion

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Application of the amplification matrix latency insertion method to circuits with dependent sources

2011 IEEE Electrical Design of Advanced Packaging and Systems Symposium (EDAPS) ◽

10.1109/edaps.2011.6213771 ◽

2011 ◽

Author(s):

Ping Liu ◽

Jilin Tan ◽

Zhongyong Zhou ◽

Jose Schutt-Aine ◽

Patrick Goh

Keyword(s):

Insertion Method ◽

Latency Insertion ◽

Dependent Sources

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Latency Insertion Method with Variable Time Step

2019 Electrical Design of Advanced Packaging and Systems (EDAPS) ◽

10.1109/edaps47854.2019.9011649 ◽

2019 ◽

Author(s):

Gene Shiue ◽

Jose E. Schutt-Aine ◽

Patrick Goh

Keyword(s):

Time Step ◽

Variable Time ◽

Insertion Method ◽

Latency Insertion ◽

Variable Time Step

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Latency Insertion Method Based Real-Time Simulation of Power Electronic Systems

IEEE Transactions on Power Electronics ◽

10.1109/tpel.2017.2757449 ◽

2018 ◽

Vol 33 (8) ◽

pp. 7166-7177 ◽

Author(s):

Matthew Milton ◽

Andrea Benigni

Keyword(s):

Real Time ◽

Electronic Systems ◽

Power Electronic ◽

Real Time Simulation ◽

Time Simulation ◽

Insertion Method ◽

Latency Insertion

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Predictor-corrector latency insertion method for fast transient analysis of ill-constructed circuits

17th Asia and South Pacific Design Automation Conference ◽

10.1109/aspdac.2012.6164975 ◽

2012 ◽

Author(s):

Hiroki Kurobe ◽

Tadatoshi Sekine ◽

Hideki Asai

Keyword(s):

Transient Analysis ◽

Insertion Method ◽

Latency Insertion ◽

Fast Transient ◽

Predictor Corrector

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Nonlinear block latency insertion method for fast simulation of strongly coupled network with CMOS inverters

2011 IEEE Electrical Design of Advanced Packaging and Systems Symposium (EDAPS) ◽

10.1109/edaps.2011.6213772 ◽

2011 ◽

Author(s):

Y. Hizawa ◽

H. Kurobe ◽

T. Sekine ◽

H. Asai

Keyword(s):

Fast Simulation ◽

Strongly Coupled ◽

Insertion Method ◽

Latency Insertion

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