An on-chip instruction cache design with one-bit tag for low-power embedded systems

In the last years, embedded systems have evolved so that they offer capabilities we could only find before in high performance systems. Portable devices already have multiprocessors on-chip (such as PowerPC 476FP or ARM Cortex A9 MP), usually multi-threaded, and a powerful multi-level cache memory hierarchy on-chip. As most of these systems are battery-powered, the power consumption becomes a critical issue. Achieving high performance and low power consumption is a high complexity challenge where some proposals have been already made. Suarez et al. proposed a new cache hierarchy on-chip, the LP-NUCA (Low Power NUCA), which is able to reduce the access latency taking advantage of NUCA (Non-Uniform Cache Architectures) properties. The key points are decoupling the functionality, and utilizing three specialized networks on-chip. This structure has been proved to be efficient for data hierarchies, achieving a good performance and reducing the energy consumption. On the other hand, instruction caches have different requirements and characteristics than data caches, contradicting the low-power embedded systems requirements, especially in SMT (simultaneous multi-threading) environments. We want to study the benefits of utilizing small tiled caches for the instruction hierarchy, so we propose a new design, ID-LP-NUCAs. Thus, we need to re-evaluate completely our previous design in terms of structure design, interconnection networks (including topologies, flow control and routing), content management (with special interest in hardware/software content allocation policies), and structure sharing. In CMP environments (chip multiprocessors) with parallel workloads, coherence plays an important role, and must be taken into consideration.

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A Low-Power Instruction Cache Design Based on Record Buffer

Journal of Computer Research and Development ◽

10.1360/crad20060426 ◽

2006 ◽

Vol 43 (4) ◽

pp. 744

Author(s):

Zhiqiang Ma

Keyword(s):

Low Power ◽

Instruction Cache ◽

Cache Design

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Low power instruction cache design based on branch execution tracks

2013 IEEE 10th International Conference on ASIC ◽

10.1109/asicon.2013.6811822 ◽

2013 ◽

Author(s):

Quanquan Li ◽

Qi Wang ◽

Tiejun Zhang ◽

Donghui Wang ◽

Chaohuan Hou

Keyword(s):

Low Power ◽

Instruction Cache ◽

Cache Design

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A Buffered Dual-Access-Mode Scheme Designed for Low-Power Highly-Associative Caches

International Journal of Embedded and Real-Time Communication Systems ◽

10.4018/jertcs.2013040103 ◽

2013 ◽

Vol 4 (2) ◽

pp. 50-61

Author(s):

Yul Chu ◽

Marven Calagos

Keyword(s):

Embedded Systems ◽

Power Consumption ◽

Low Power ◽

Access Time ◽

Data Cache ◽

Instruction Cache ◽

Prediction Mode ◽

Access Mode ◽

Cache Scheme ◽

Better Than

This paper proposes a buffered dual-access-mode cache to reduce power consumption for highly-associative caches in modern embedded systems. The proposed scheme consists of a MRU (most recently used) buffer table and a single cache structure to implement two accessing modes, phased mode and way-prediction mode. The proposed scheme shows better access time and lower power consumption than two popular low-power caches, phased cache and way-prediction cache. The authors used Cacti and SimpleScalar simulators to evaluate the proposed cache scheme by using SPEC benchmark programs. The experimental results show that the proposed cache scheme improves the EDP (energy delay product) up to 40% for instruction cache and up to 42% for data cache compared to way-prediction cache, which performs better than phased cache.

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Industrial Applications of Emulation Techniques for the Early Evaluation of Secure Low-Power Embedded Systems

Advances in Systems Analysis, Software Engineering, and High Performance Computing - Handbook of Research on Embedded Systems Design ◽

10.4018/978-1-4666-6194-3.ch013 ◽

2014 ◽

pp. 328-346

Author(s):

Norbert Druml ◽

Manuel Menghin ◽

Christian Steger ◽

Armin Krieg ◽

Andreas Genser ◽

...

Keyword(s):

Embedded Systems ◽

Low Power ◽

Network Models ◽

Industrial Applications ◽

Early Evaluation ◽

Traditional System ◽

Verification Time ◽

On Chip ◽

High Level ◽

Verification Methodology

Embedded systems that follow a secure and low-power design methodology are, besides keeping strict design constraints, heavily dependent on comprehensive test and verification procedures. The large set of possible test vectors and the increasing density of System-on-Chip designs call for the introduction of hardware-accelerated techniques to solve the verification time problem. As already described earlier, emulation-based methodologies based on FPGA evaluation platforms prove capable of providing a solution compared to traditional system simulation. This chapter gives an introduction into a multi-disciplinary emulation-based design evaluation and verification methodology that is based on various techniques that have been presented in chapter 5. Test and verification capabilities are enhanced by the augmentation of this approach using model-based analysis units: gate-level-based power consumption models, power supply network models, event-based performance monitors, and high-level fault modes. The feasible usage of this verification methodology in the field of contactlessly powered smart cards is finally demonstrated using several industrial case studies.

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