MOS transistor mismatch modelling for high voltage CMOS processes

IEEE/SEMI Conference and Workshop on Advanced Semiconductor Manufacturing 2005. ◽

10.1109/asmc.2005.1438805 ◽

2005 ◽

Author(s):

Werner Posch ◽

Gerhard Rappitsch ◽

Georg Leonardelli

Keyword(s):

High Voltage ◽

Mos Transistor ◽

Transistor Mismatch ◽

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Statistical Modelling of MOS Transistor Mismatch for High-voltage CMOS Processes

Quality and Reliability Engineering International ◽

10.1002/qre.735 ◽

2005 ◽

Vol 21 (5) ◽

pp. 477-489 ◽

Author(s):

Werner Posch ◽

Hubert Enichlmair ◽

Eduard Schirgi ◽

Gerhard Rappitsch

Keyword(s):

High Voltage ◽

Statistical Modelling ◽

Mos Transistor ◽

Transistor Mismatch ◽

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Statistical modeling of MOS transistor mismatch based on the parameters' autocorrelation function

ISCAS'99. Proceedings of the 1999 IEEE International Symposium on Circuits and Systems VLSI (Cat. No.99CH36349) ◽

10.1109/iscas.1999.780135 ◽

2003 ◽

Author(s):

M. Conti ◽

P. Crippa ◽

S. Orcioni ◽

C. Turchetti

Keyword(s):

Statistical Modeling ◽

Autocorrelation Function ◽

Mos Transistor ◽

Transistor Mismatch

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An RC-triggered ESD clamp for high-voltage BCD CMOS processes

TURKISH JOURNAL OF ELECTRICAL ENGINEERING & COMPUTER SCIENCES ◽

10.3906/elk-1610-49 ◽

2017 ◽

Vol 25 ◽

pp. 3435-3442

Author(s):

Fatih KOÇER

Keyword(s):

High Voltage ◽

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Design of High-Voltage-Tolerant Power-Rail ESD Protection Circuit for Power Pin of Negative Voltage in Low-Voltage CMOS Processes

IEEE Transactions on Electron Devices ◽

10.1109/ted.2019.2954754 ◽

2020 ◽

Vol 67 (1) ◽

pp. 40-46

Author(s):

Rong-Kun Chang ◽

Ming-Dou Ker

Keyword(s):

High Voltage ◽

Low Voltage ◽

Negative Voltage ◽

Esd Protection ◽

Protection Circuit ◽

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A methodology for MOS transistor mismatch parameter extraction and mismatch simulation

2000 IEEE International Symposium on Circuits and Systems. Emerging Technologies for the 21st Century. Proceedings (IEEE Cat No.00CH36353) ◽

10.1109/iscas.2000.858700 ◽

2002 ◽

Author(s):

T. Serrano-Gotarredona ◽

B. Linares-Barranco

Keyword(s):

Parameter Extraction ◽

Mos Transistor ◽

Transistor Mismatch

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The impact of short channel and quantum effects on the MOS transistor mismatch

Solid-State Electronics ◽

10.1016/s0038-1101(03)00033-9 ◽

2003 ◽

Vol 47 (7) ◽

pp. 1161-1165 ◽

Author(s):

R Difrenza ◽

P Llinares ◽

G Ghibaudo

Keyword(s):

Quantum Effects ◽

Short Channel ◽

Mos Transistor ◽

Transistor Mismatch ◽

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High-voltage structure of MOS transistor for LCD driver circuits application

10.1117/12.131312 ◽

1992 ◽

Author(s):

Kun-Zen Chang ◽

Jinnu-Fu Liou ◽

Mei-Li Chiou ◽

S. W. Chang

Keyword(s):

High Voltage ◽

Mos Transistor ◽

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High-voltage DSA-MOS transistor for electroluminescent display

10.1109/isscc.1978.1155781 ◽

1978 ◽

Author(s):

K. Awane ◽

K. Fujii ◽

T. Yamano ◽

H. Tamaki ◽

T. Biwa ◽

...

Keyword(s):

High Voltage ◽

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A new five-parameter MOS transistor mismatch model

IEEE Electron Device Letters ◽

10.1109/55.817445 ◽

2000 ◽

Vol 21 (1) ◽

pp. 37-39 ◽

Author(s):

T. Serrano-Gotarredona ◽

B. Linares-Barranco

Keyword(s):

Mos Transistor ◽

Transistor Mismatch

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Design of High-Voltage-Tolerant Power-Rail ESD Clamp Circuit in Low-Voltage CMOS Processes

2007 IEEE International Reliability Physics Symposium Proceedings. 45th Annual ◽

10.1109/relphy.2007.369967 ◽

2007 ◽

Author(s):

Ming-Dou Ker ◽

Chang-Tzu Wang ◽

Tien-Hao Tang ◽

Kuan-Cheng Su

Keyword(s):

High Voltage ◽

Low Voltage ◽

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