scholarly journals An Asynchronous SDM Network-on-Chip Tolerating Permanent Faults

2014 ◽  
Author(s):  
Guangda Zhang ◽  
Wei Song ◽  
Jim Garside ◽  
Javier Navaridas ◽  
Zhiying Wang
Keyword(s):  
Network On Chip ◽  
Permanent Faults ◽  
On Chip

scholarly journals Tolerating Permanent Faults in the Input Port of the Network on Chip Router

2019 ◽  
Vol 9 (1) ◽  
pp. 11 ◽  
Author(s):  
Hala Mohammed ◽  
Wameedh Flayyih ◽  
Fakhrul Rokhani
Keyword(s):  
Network Performance ◽  
Deep Submicron ◽  
Network On Chip ◽  
Input Port ◽  
Virtual Channel ◽  
Transient Faults ◽  
Single Chip ◽  
Permanent Faults ◽  
Hardware Redundancy ◽  
On Chip

Deep submicron technologies continue to develop according to Moore’s law allowing hundreds of processing elements and memory modules to be integrated on a single chip forming multi/many-processor systems-on-chip (MPSoCs). Network on chip (NoC) arose as an interconnection for this large number of processing modules. However, the aggressive scaling of transistors makes NoC more vulnerable to both permanent and transient faults. Permanent faults persistently affect the circuit functionality from the time of their occurrence. The router represents the heart of the NoC. Thus, this research focuses on tolerating permanent faults in the router’s input buffer component, particularly the virtual channel state fields. These fields track packets from the moment they enter the input component until they leave to the next router. The hardware redundancy approach is used to tolerate the faults in these fields due to their crucial role in managing the router operation. A built-in self-test logic is integrated into the input port to periodically detect permanent faults without interrupting router operation. These approaches make the NoC router more reliable than the unprotected NoC router with a maximum of 17% and 16% area and power overheads, respectively. In addition, the hardware redundancy approach preserves the network performance in the presence of a single fault by avoiding the virtual channel closure.

VLSI Design Of Low Energy Modeling For Network On Chip (NoC) Applications

2014 ◽  
Vol 5 (1) ◽  
pp. 27-32
Author(s):  
Jeeva Anusha ◽  
◽  
V. Thrimurthulu ◽  
Keyword(s):  
Vlsi Design ◽  
Network On Chip ◽  
Energy Modeling ◽  
Low Energy ◽  
On Chip

Pre-allocated Path Based Low Latency Router Architecture for Network-on-chip

2014 ◽  
Vol 35 (2) ◽  
pp. 341-346
Author(s):  
Xiao-fu Zheng ◽  
Hua-xi Gu ◽  
Yin-tang Yang ◽  
Zhong-fan Huang
Keyword(s):  
Network On Chip ◽  
Low Latency ◽  
Router Architecture ◽  
On Chip

An optimized path-setup method for mesh based Optical Network on Chip

2015 ◽  
Author(s):  
Wei Tan ◽  
Bowen Zhang ◽  
Huaxi Gu ◽  
Zheng Chen
Keyword(s):  
Optical Network ◽  
Network On Chip ◽  
On Chip
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