scholarly journals Tolerating Permanent Faults in the Input Port of the Network on Chip Router

2019 ◽  
Vol 9 (1) ◽  
pp. 11 ◽  
Author(s):  
Hala Mohammed ◽  
Wameedh Flayyih ◽  
Fakhrul Rokhani
Keyword(s):  
Network Performance ◽  
Deep Submicron ◽  
Network On Chip ◽  
Input Port ◽  
Virtual Channel ◽  
Transient Faults ◽  
Single Chip ◽  
Permanent Faults ◽  
Hardware Redundancy ◽  
On Chip

Deep submicron technologies continue to develop according to Moore’s law allowing hundreds of processing elements and memory modules to be integrated on a single chip forming multi/many-processor systems-on-chip (MPSoCs). Network on chip (NoC) arose as an interconnection for this large number of processing modules. However, the aggressive scaling of transistors makes NoC more vulnerable to both permanent and transient faults. Permanent faults persistently affect the circuit functionality from the time of their occurrence. The router represents the heart of the NoC. Thus, this research focuses on tolerating permanent faults in the router’s input buffer component, particularly the virtual channel state fields. These fields track packets from the moment they enter the input component until they leave to the next router. The hardware redundancy approach is used to tolerate the faults in these fields due to their crucial role in managing the router operation. A built-in self-test logic is integrated into the input port to periodically detect permanent faults without interrupting router operation. These approaches make the NoC router more reliable than the unprotected NoC router with a maximum of 17% and 16% area and power overheads, respectively. In addition, the hardware redundancy approach preserves the network performance in the presence of a single fault by avoiding the virtual channel closure.

scholarly journals Virtual channel organization and arbitration for network on chip router architecure

2021 ◽  
Author(s):  
Masoud Oveis Gharan
Keyword(s):  
Network On Chip ◽  
Input Port ◽  
Virtual Channel ◽  
Chip Area ◽  
Theoretical Concepts ◽  
Real Time Traffic ◽  
Systems On Chip ◽  
Physical Channel ◽  
And Performance ◽  
On Chip

The advent of Multi-Processor Systems-on-Chip (MPSoC) has emphasized the importance of on-chip communication infrastructures. Network on Chip (NoC) has emerged as a state of the art paradigm for efficient on-chip communication. Among the various components employed in NoC routers, Virtual Channel (VC) plays an important role in the performance and hardware requirements of an NoC system. The VC mechanism enables the multiplexing and buffering of several packets to travel over a single physical channel concurrently. VC arbitration (or arbiter) is another critical organization component of a router that has significant impact on the efficiency of an NoC system. Arbiter performs arbitration among the group of VCs that are competing for a single resource (e.g. output-port). In this dissertation, we propose novel approaches for dynamic VC flow control mechanism and VC arbitration. The first two approaches are based on the adaptivity of VCs in the router input-port that improves the efficiency of NoC system. In both of techniques, the input-port comprises of a centralized buffer whose slots are dynamically allocated to VCs according to a real-time traffic situation. The performance improvement is achieved by utilizing multiple virtual channels with minimal buffer resources. The VC arbitration approach is based on an efficient and fast arbiter that functions upon the index of its input-ports (or VC requests). The architecture of arbiter scales with the Log2 of the number of inputs where a conventional round robin arbiter scales with the number of inputs. The index based behavior and the architecture of our arbiter leads to lower power consumption and chip area. This dissertation presents the organizations and micro-architectures of NoC routers. We have employed SystemVerilog at the micro-architectural level design and modeling of NoC components. We employ three CAD platforms namely ModelSim, Quartus (FPGA) and Synopsys (ASIC level) to design, simulate and implement our router based NoCs. The simulation results support the theoretical concepts of our proposed VC organization and arbitration approaches. We have also implemented and conducted simulation and modeling experiments for conventional VC organization and arbitration models. The experimental results verify the efficiency of our proposed models in terms of power, area and performance in different NoC configurations.

scholarly journals Virtual channel organization and arbitration for network on chip router architecure

2021 ◽  
Author(s):  
Masoud Oveis Gharan
Keyword(s):  
Network On Chip ◽  
Input Port ◽  
Virtual Channel ◽  
Chip Area ◽  
Theoretical Concepts ◽  
Real Time Traffic ◽  
Systems On Chip ◽  
Physical Channel ◽  
And Performance ◽  
On Chip

The advent of Multi-Processor Systems-on-Chip (MPSoC) has emphasized the importance of on-chip communication infrastructures. Network on Chip (NoC) has emerged as a state of the art paradigm for efficient on-chip communication. Among the various components employed in NoC routers, Virtual Channel (VC) plays an important role in the performance and hardware requirements of an NoC system. The VC mechanism enables the multiplexing and buffering of several packets to travel over a single physical channel concurrently. VC arbitration (or arbiter) is another critical organization component of a router that has significant impact on the efficiency of an NoC system. Arbiter performs arbitration among the group of VCs that are competing for a single resource (e.g. output-port). In this dissertation, we propose novel approaches for dynamic VC flow control mechanism and VC arbitration. The first two approaches are based on the adaptivity of VCs in the router input-port that improves the efficiency of NoC system. In both of techniques, the input-port comprises of a centralized buffer whose slots are dynamically allocated to VCs according to a real-time traffic situation. The performance improvement is achieved by utilizing multiple virtual channels with minimal buffer resources. The VC arbitration approach is based on an efficient and fast arbiter that functions upon the index of its input-ports (or VC requests). The architecture of arbiter scales with the Log2 of the number of inputs where a conventional round robin arbiter scales with the number of inputs. The index based behavior and the architecture of our arbiter leads to lower power consumption and chip area. This dissertation presents the organizations and micro-architectures of NoC routers. We have employed SystemVerilog at the micro-architectural level design and modeling of NoC components. We employ three CAD platforms namely ModelSim, Quartus (FPGA) and Synopsys (ASIC level) to design, simulate and implement our router based NoCs. The simulation results support the theoretical concepts of our proposed VC organization and arbitration approaches. We have also implemented and conducted simulation and modeling experiments for conventional VC organization and arbitration models. The experimental results verify the efficiency of our proposed models in terms of power, area and performance in different NoC configurations.

Task mapping and scheduling for network-on-chip based multi-core platform with transient faults

2018 ◽  
Vol 83 ◽  
pp. 34-56 ◽  
Author(s):  
Navonil Chatterjee ◽  
Suraj Paul ◽  
Santanu Chattopadhyay
Keyword(s):  
Network On Chip ◽  
Task Mapping ◽  
Transient Faults ◽  
On Chip

An Internal Schematic View and Simulation of Major Diagonal Mesh Network-on-Chip

2019 ◽  
Vol 16 (10) ◽  
pp. 4412-4417 ◽  
Author(s):  
Sanjeev Kumar Sharma ◽  
Arpit Jain ◽  
Kamali Gupta ◽  
Devendra Prasad ◽  
Varinder Singh
Keyword(s):  
Network On Chip ◽  
Mesh Network ◽  
Network Architectures ◽  
Memory Usage ◽  
Semantic View ◽  
Single Chip ◽  
Register Transfer ◽  
On Chip ◽  
High Congestion

NoC is a competent communication for on chip network architectures. It make more efficient the computational and high congestion communication on a single chip. In this paper, we are proposing a NoC topologies, i.e., Major Diagonal Mesh NoC called MD-Mesh NoC. In MD-Mesh NoC the corner of major diagonal linked with each other so that the efficiency of the communication among the corner can be increase. The internal semantic view and register transfer logic (RTL) View has been shown. As number of connections among the nodes increases and number of hopes decreases, performance of packet traversing will get increases. The synthesis and simulation has been done on Vertex 5 FPGA. The hardware parameters like number of slices and memory usage with respect to increase the number of nodes has been calculated on FPGA Vertex 5.

scholarly journals Cooperative virtual channel router for adaptive hardwired FPGA network-on-chip

2016 ◽  
Author(s):  
F.F Zakaria ◽  
Naa Latif ◽  
Shaiful Jahari Hashim ◽  
P. Ehkan ◽  
F.Z. Rokhani
Keyword(s):  
Network On Chip ◽  
Virtual Channel ◽  
On Chip
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