CMOS image sensor camera with focal plane edge detection

This paper presents a CMOS image sensor (CIS) with built-in lane detection computing circuits for automotive applications. We propose on-CIS processing with an edge detection mask used in the readout circuit of the conventional CIS structure for high-speed lane detection. Furthermore, the edge detection mask can detect the edges of slanting lanes to improve accuracy. A prototype of the proposed CIS was fabricated using a 110 nm CIS process. It has an image resolution of 160 (H) × 120 (V) and a frame rate of 113, and it occupies an area of 5900 μm × 5240 μm. A comparison of its lane detection accuracy with that of existing edge detection algorithms shows that it achieves an acceptable accuracy. Moreover, the total power consumption of the proposed CIS is 9.7 mW at pixel, analog, and digital supply voltages of 3.3, 3.3, and 1.5 V, respectively.

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A row-parallel cyclic-line-access edge detection CMOS image sensor employing global thresholding operation

Proceedings of 2010 IEEE International Symposium on Circuits and Systems ◽

10.1109/iscas.2010.5537512 ◽

2010 ◽

Cited By ~ 2

Author(s):

Norihiro Takahashi ◽

Tadashi Shibata

Keyword(s):

Edge Detection ◽

Cmos Image Sensor ◽

Image Sensor ◽

Global Thresholding

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Design of an Edge-Detection CMOS Image Sensor with Built-in Mask Circuits

Sensors ◽

10.3390/s20133649 ◽

2020 ◽

Vol 20 (13) ◽

pp. 3649

Author(s):

Minhyun Jin ◽

Hyeonseob Noh ◽

Minkyu Song ◽

Soo Youn Kim

Keyword(s):

Power Consumption ◽

Edge Detection ◽

Low Power ◽

High Speed ◽

Cmos Image Sensor ◽

Image Sensor ◽

Frame Rate ◽

Oxide Semiconductor ◽

Total Power ◽

Total Power Consumption

In this paper, we propose a complementary metal-oxide-semiconductor (CMOS) image sensor (CIS) that has built-in mask circuits to selectively capture either edge-detection images or normal 8-bit images for low-power computer vision applications. To detect the edges of images in the CIS, neighboring column data are compared in in-column memories after column-parallel analog-to-digital conversion with the proposed mask. The proposed built-in mask circuits are implemented in the CIS without a complex image signal processer to obtain edge images with high speed and low power consumption. According to the measurement results, edge images were successfully obtained with a maximum frame rate of 60 fps. A prototype sensor with 1920 × 1440 resolution was fabricated with a 90-nm 1-poly 5-metal CIS process. The area of the 4-shared 4T-active pixel sensor was 1.4 × 1.4 µm2, and the chip size was 5.15 × 5.15 mm2. The total power consumption was 9.4 mW at 60 fps with supply voltages of 3.3 V (analog), 2.8 V (pixel), and 1.2 V (digital).

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