On-CMOS Image Sensor Processing for Lane Detection

This paper presents a CMOS image sensor (CIS) with built-in lane detection computing circuits for automotive applications. We propose on-CIS processing with an edge detection mask used in the readout circuit of the conventional CIS structure for high-speed lane detection. Furthermore, the edge detection mask can detect the edges of slanting lanes to improve accuracy. A prototype of the proposed CIS was fabricated using a 110 nm CIS process. It has an image resolution of 160 (H) × 120 (V) and a frame rate of 113, and it occupies an area of 5900 μm × 5240 μm. A comparison of its lane detection accuracy with that of existing edge detection algorithms shows that it achieves an acceptable accuracy. Moreover, the total power consumption of the proposed CIS is 9.7 mW at pixel, analog, and digital supply voltages of 3.3, 3.3, and 1.5 V, respectively.

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Design of an Edge-Detection CMOS Image Sensor with Built-in Mask Circuits

Sensors ◽

10.3390/s20133649 ◽

2020 ◽

Vol 20 (13) ◽

pp. 3649

Author(s):

Minhyun Jin ◽

Hyeonseob Noh ◽

Minkyu Song ◽

Soo Youn Kim

Keyword(s):

Power Consumption ◽

Edge Detection ◽

Low Power ◽

High Speed ◽

Cmos Image Sensor ◽

Image Sensor ◽

Frame Rate ◽

Oxide Semiconductor ◽

Total Power ◽

Total Power Consumption

In this paper, we propose a complementary metal-oxide-semiconductor (CMOS) image sensor (CIS) that has built-in mask circuits to selectively capture either edge-detection images or normal 8-bit images for low-power computer vision applications. To detect the edges of images in the CIS, neighboring column data are compared in in-column memories after column-parallel analog-to-digital conversion with the proposed mask. The proposed built-in mask circuits are implemented in the CIS without a complex image signal processer to obtain edge images with high speed and low power consumption. According to the measurement results, edge images were successfully obtained with a maximum frame rate of 60 fps. A prototype sensor with 1920 × 1440 resolution was fabricated with a 90-nm 1-poly 5-metal CIS process. The area of the 4-shared 4T-active pixel sensor was 1.4 × 1.4 µm2, and the chip size was 5.15 × 5.15 mm2. The total power consumption was 9.4 mW at 60 fps with supply voltages of 3.3 V (analog), 2.8 V (pixel), and 1.2 V (digital).

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A CMOS Image Sensor with a Novel Passive Pixel Array and High Precision Current Amplifier for a Compact Digital X-ray Detector

Journal of Medical Imaging and Health Informatics ◽

10.1166/jmihi.2020.3210 ◽

2020 ◽

Vol 10 (11) ◽

pp. 2745-2753

Author(s):

Jimin Cheon ◽

Dongmyung Lee ◽

Hojong Choi

Keyword(s):

High Precision ◽

Dynamic Range ◽

Cmos Image Sensor ◽

Image Sensor ◽

Total Power ◽

Cmos Process ◽

Current Amplifier ◽

X Ray ◽

Total Power Consumption ◽

Pixel Array

An active pixel sensor (APS) in a digital X-ray detector is the dominant circuitry for a CMOS image sensor (CIS) despite its lower fill factor (FF) compared to that of a passive pixel sensor (PPS). Although the PPS provides higher FF, its overall signal-to-noise ratio (SNR) is lower than that of the APS. The required high resolution and small focal plane can be achieved by reducing the number of transistors and contacts per pixel. We proposed a novel passive pixel array and a high precision current amplifier to improve the dynamic range (DR) without minimizing the sensitivity for diagnostic compact digital X-ray detector applications. The PPS can be an alternative to improve the FF. However, size reduction of the feedback capacitor causes degradation of SNR performance. This paper proposes a novel PPS based on readout and amplification circuits with a high precision current amplifier to minimize performance degradation. The expected result was attained with a 0.35-μm CMOS process parameter with power supply voltage of 3.3 V. The proposed PPS has a saturation signal of 1.5 V, dynamic range of 63.5 dB, and total power consumption of 13.47 mW. Therefore, the proposed PPS readout circuit improves the dynamic range without sacrificing the sensitivity.

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Design of an Always-On Image Sensor Using an Analog Lightweight Convolutional Neural Network

Sensors ◽

10.3390/s20113101 ◽

2020 ◽

Vol 20 (11) ◽

pp. 3101

Author(s):

Jaihyuk Choi ◽

Sungjae Lee ◽

Youngdoo Son ◽

Soo Youn Kim

Keyword(s):

Neural Network ◽

Power Consumption ◽

Convolutional Neural Network ◽

Image Classification ◽

Image Sensor ◽

Image Resolution ◽

Oxide Semiconductor ◽

Total Power ◽

Max Pooling ◽

Total Power Consumption

This paper presents an always-on Complementary Metal Oxide Semiconductor (CMOS) image sensor (CIS) using an analog convolutional neural network for image classification in mobile applications. To reduce the power consumption as well as the overall processing time, we propose analog convolution circuits for computing convolution, max-pooling, and correlated double sampling operations without operational transconductance amplifiers. In addition, we used the voltage-mode MAX circuit for max pooling in the analog domain. After the analog convolution processing, the image data were reduced by 99.58% and were converted to digital with a 4-bit single-slope analog-to-digital converter. After the conversion, images were classified by the fully connected processor, which is traditionally performed in the digital domain. The measurement results show that we achieved an 89.33% image classification accuracy. The prototype CIS was fabricated in a 0.11 μm 1-poly 4-metal CIS process with a standard 4T-active pixel sensor. The image resolution was 160 × 120, and the total power consumption of the proposed CIS was 1.12 mW with a 3.3 V supply voltage and a maximum frame rate of 120.

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14-Bit Fully Differential SAR ADC with PGA Used in Readout Circuit of CMOS Image Sensor

Journal of Sensors ◽

10.1155/2021/6651642 ◽

2021 ◽

Vol 2021 ◽

pp. 1-17

Author(s):

Xiaowei Zhang ◽

Wei Fan ◽

Jianxiong Xi ◽

Lenian He

Keyword(s):

Sampling Rate ◽

Cmos Image Sensor ◽

Image Sensor ◽

Sar Adc ◽

Total Power ◽

Cmos Process ◽

Readout Circuit ◽

Fully Differential ◽

Total Power Consumption ◽

The Impact

This paper proposes a 14-bit fully differential Successive Approximation Register (SAR) Analog-to-Digital Converter (ADC) with a programmable gain amplifier (PGA) used in the readout circuit of CMOS image sensor (CIS). SAR ADC adopts two-step scaled-reference voltages to realize 14-bit conversion, aimed at reducing the scale of capacitor array and avoiding using calibration to mitigate the impact of offset and mismatch. However, the reference voltage self-calibration algorithm is applied on the design to guarantee the precision of reference voltages, which affects the results of conversion. The three-way PGA provides three types of gains: 3x, 4x, and 6x, and samples at the same time to get three columns of pixel signal and increase the system speed. The pixel array of the mentioned CIS is 1026 × 1024 , and the pixel pitch is 12.5 μ m × 12.5 μ m . The prototype chip is fabricated in the 180 nm CMOS process, and both digital and analog voltages are 3.3 V. The total area of the chip is 6.25 × 18.38 mm2. At 150 kS/s sampling rate, the SNR of SAR ADC is 71.72 dB and the SFDR is 82.91 dB. What is more, the single SAR ADC consumes 477.2 uW with the 4.8 V PP differential input signal and the total power consumption of the CIS is about 613 mW.

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Over 100 Million Frames per Second 368 Frames Global Shutter Burst CMOS Image Sensor with Pixel-wise Trench Capacitor Memory Array

Sensors ◽

10.3390/s20041086 ◽

2020 ◽

Vol 20 (4) ◽

pp. 1086 ◽

Cited By ~ 2

Author(s):

Manabu Suzuki ◽

Yuki Sugama ◽

Rihito Kuroda ◽

Shigetoshi Sugawa

Keyword(s):

High Speed ◽

Cooling System ◽

Complementary Metal Oxide Semiconductor ◽

Cmos Image Sensor ◽

Image Sensor ◽

Frame Rate ◽

Oxide Semiconductor ◽

Photoelectric Conversion ◽

Memory Array ◽

Record Length

In this paper, a prototype ultra-high speed global shutter complementary metal-oxide-semiconductor (CMOS) image sensor with pixel-wise trench capacitor memory array achieving over 100 million frames per second (fps) with up to 368 record length by burst correlated double sampling (CDS) operation is presented. Over 100 Mfps high frame rate is obtained by reduction of pixel output load by the pixel-wise memory array architecture and introduction of the burst CDS operation which minimizes the pixel driving pulse transitions. Long record length is realized by high density analog memory integration with Si trench capacitors. A maximum 125 Mfps frame rate with up to 368 record length video capturing was confirmed under room temperature without any cooling system. The photoelectric conversion characteristics of the burst CDS operation were measured and compared with those of the conventional CDS operation.

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