High Efficient Virtual Machine Migration Using Glow Worm Swarm Optimization Method for Cloud Computing

In this paper, high efficient Virtual Machine (VM) migration using GSO algorithm for cloud computing is proposed. This algorithm contains 3 phases: (i) VM selection, (ii) optimum number of VMs selection, (iii) VM placement. In VM selection phase, VMs to be migrated are selected based on their resource utilization and fault probability. In phase-2, optimum number of VMs to be migrated are determined based on the total power consumption. In VM placement phase, Glowworm Swarm Optimization (GSO) is used for finding the target VMs to place the migrated VMs. The fitness function is derived in terms of distance between the main server and the other server, VM capacity and memory size. Then the VMs with best fitness functions are selected as target VMs for placing the migrated VMs. The proposed algorithms are implemented in Cloudsim and performance results show that PEVM-GSO algorithm attains reduced power consumption and response delay with improved CPU utilization.

Joint Power and Subchannel Allocation for Distributed Storage in Cellular-D2D Underlays

Wireless distributed storage is beneficial in the provision of reliable content storage and offloading of cellular traffic. In this paper, we consider a cellular device-to-device (D2D) underlay-based wireless distributed storage system, in which the minimum storage regenerating (MSR) coding combined with the partial downloading scheme is employed. To alleviate burdens on insufficient cellular resources and improve spectral efficiency in densely deployed networks, multiple storage devices can simultaneously use the same uplink cellular subchannel under the non-orthogonal multiple access (NOMA) protocol. Our objective is to minimize the total transmission power for content reconstruction, while guaranteeing the signal-to-interference-plus-noise ratio (SINR) constraints for cellular users by jointly optimizing power and subchannel allocation. To tackle the non-convex combinational program, we decouple the original problem into two subproblems and propose two low-complexity algorithms to efficiently solve them, followed by a joint optimization, implemented by alternately updating the solutions to each subproblem. The numerical results illustrate that our proposed algorithms are capable of performing an exhaustive search with lower computation complexity, and the NOMA-enhanced scheme provides more transmission opportunities for neighbor storage devices, thus significantly reducing the total power consumption.

Techno-Economic Analysis of the Reclamation of Drinking Water and Valuable Minerals from Acid Mine Drainage

The concept of circular economy in wastewater treatment has recently attracted immense interest and this is primarily fueled by the ever-growing interest to minimise ecological footprints of mining activities and metallurgical processes. In light of that, countries such as the Republic of South Africa, China, Australia, and the United States are at the forefront of water pollution due to the generation of notorious acid mine drainage (AMD). The disposal of AMD to different receiving environments constitutes a severe threat to the receiving ecosystem thus calling for prudent intervention to redress the prevailing challenges. Recent research emphasises the employment of wastewater treatment, beneficiation and valorisation. Herein, the techno-economic evaluation of the reclamation of clean water and valuable minerals from AMD using the Magnesite Softening and Reverse Osmosis (MASRO) process was reported. The total capital expenditure (CAPEX) for the plant is ZAR 452,000 (USD 31,103.22) which includes ZAR 110,000 (USD 7569.37) for civil works on a plant area of 100 m2. The operational expenditure (OPEX) for the pilot is 16,550,000 ZAR (South African Rand) or USD 1,138,845.72 in present value terms (10 years plant life). The plant reclaimed drinking water as specified in different water quality standards, guidelines, and specifications, including Fe-based minerals (goethite, magnetite, and hematite), Mg-gypsum, and calcium carbonate. These minerals were verified using state-of-the-art analytical equipment. The recovered valuables will be sold at ZAR 368/kL (USD 25.32), ZAR 1100/t (USD 75.69), and ZAR 2000/t (USD 137.62) for water, gypsum, and limestone, respectively. The project has an NPV of ZAR 60,000 (USD 4128.75) at an IRR of 26%. The payback period for this investment will take 3 years. The total power consumption per day was recorded to be 146.6 kWh, and 103,288 kWh/annum. In conclusion, findings of this work will significantly contribute to improving the sustainability of the mining sector by proposing economically feasible solutions for wastewater streams treatment, beneficiation, and valorisation.

VLSI Implementation of Green Computing Control Unit on Zynq FPGA for Green Communication

The issue of the energy shortage is affecting the entire planet. This is occurring because of massive population and industry growth around the world. As a result, the entire world is attempting to implement green networking systems and manufacture the power/energy efficient products. This research work discusses the green networking system technologies. This work introduces a power-efficient control unit (CU) design and implemented on the Zynq SoC (System on Chip) ultrascale field programmable gate array (FPGA). The VIVADO HLx Design Suite is used to simulate and analyze the CU model which is considered as one of the key components of central processing unit (CPU), used for data communication purposes. The CU is made suitable for the green communication by making it power-efficient. Therefore, the power consumption of the CU is analyzed for the various set frequency value ranging between 100 MHz and 5 GHz, and it is discovered that as the clock frequency rises up, the total power consumption also tends to get increased. The total power of the proposed model is reduced by 77.42%, 21.29%, and 17.93% from three models, respectively, being compared in the present paper. Final results shows that the CU is better suited to run at low frequencies to optimize power consumption.

Low-Threshold, High-Power On-Chip Tunable III-V/Si Lasers with Integrated Semiconductor Optical Amplifiers

Heterogeneously integrated III-V/Si lasers and semiconductor optical amplifiers (SOAs) are key devices for integrated photonics applications requiring miniaturized on-chip light sources, such as in optical communications, sensing, or spectroscopy. In this work, we present a widely tunable laser co-integrated with a semiconductor optical amplifier in a heterogeneous platform that combines AlGaInAs multiple quantum wells (MQWs) and InP-based materials with silicon-on-insulator (SOI) wafers containing photonic integrated circuits. The co-integrated device is compact, has a total device footprint of 0.5 mm2, a lasing current threshold of 10 mA, a selectable wavelength tuning range of 50 nm centered at λ = 1549 nm, a fiber-coupled output power of 10 mW, and a laser linewidth of ν = 259 KHz. The SOA provides an on-chip gain of 18 dB/mm. The total power consumption of the co-integrated devices remains below 0.5 W even for the most power demanding lasing wavelengths. Apart from the above-mentioned applications, the co-integration of compact widely tunable III-V/Si lasers with on-chip SOAs provides a step forward towards the development of highly efficient, portable, and low power systems for wavelength division multiplexed passive optical networks (WDM-PONs).

Heating of natural gas before expander - generator unit

The article discusses the replacement of throttling at the stations of technological lowering of the pressure of main natural gas by an expander-generator technology that allows the production of a cheap one with high environmental indicators. The disadvantage of this method of generating electricity is a significant cooling of the gas at the outlet of the expander, which necessitates its heating. The efficiency of the expander-generator set is largely determined by the adopted gas heating scheme. Achieving such heating temperatures is possible only by using high-potential energy resources, which are present in the technological equipment of gas distribution stations in the form of gas heaters with an intermediate heat carrier, designed to heat gas before expansion. Calculations of the amount of fuel gas required for heating the main natural gas in front of the expander-generator unit at the gas distribution stations under consideration have been carried out. The results of the study of the influence of the temperature of gas heating in front of the expander on the consumption of fuel gas supplied for heating and the numbers of heaters are presented. An analytical dependence of the electric power of the heat pump installation on the difference between the total power consumption of the compressor and the power of the air turbine is obtained.

IMPLEMENTATION OF ELECTRONIC DEVICES OF CMOS FULL ADDER IN LOW POWER VLSI CIRCUITS

Battery-powered devices (for example, mobile phones, digital personal aids, etc) are increasing on the mobile electronic systems market by developing microelectronic circuits with low energy dissipation. The problem of dissipating power could limit the flexibility of the computer system, as the chip’s density and complexity keep on increasing. The power supply consumes approximately 35% of the chip power, particularly at the nanometer level. The purpose of this project is to investigate the efficiency of one of the most reliable low power concepts called Power Gating. It is only nanometer-scale CMOS devices that are the most common technology in existing VLSI systems. Leakage power has become an integral component of total power in the nanometer technology regime. The ALU’s basic feature unit is Full Adder. The electricity consumption of an ALU is decreased by decreasing the energy consumption of an ALU, and an ALU will reduce the power consumption by decreasing the total power consumption. So these days, the complete adder designs are becoming more common with low power characteristics. The proposed project shows the concept of the micro wind tool for low power less transistors.

Optimization Design and Analysis of Single-Stage Mixed Refrigerant Liquefaction Process

Small-scale natural gas liquefaction processes have several clear advantages, particularly in the exploitation of ‘unconventional’ natural gas (NG) from sources such as difficult-to-access and offshore gas fields. Moreover, conventional liquefaction processes have a number of disadvantages such as high energy consumption, large cooling loads required in the refrigeration cycle, and non-uniform matching of cold and hot flows in liquified natural gas (LNG) heat exchanger (HE). The main objective of this study was to optimize the most commonly used mixed refrigerant process. The liquefaction performance of the optimized process was analyzed and the influence of gas parameters on the power consumption, exergy loss, freezing mixture circulation, and cooling water load were investigated. The results show that compressor power consumption can be reduced by 29.8%, the cooling water load can be reduced by 21.3%, and the system exergy efficiency can be increased by 41% with the optimized process. Furthermore, throttling and compression of the freezing mixture were increased during the refrigeration stage. It can be concluded that reducing the feed gas temperature and increasing the feed gas pressure can reduce the total power consumption, exergy loss, freezing mixture circulation, and cooling water load, which can significantly improve liquefaction performance.

CMOS Implementation of ANNs Based on Analog Optimization of N-Dimensional Objective Functions

The design of neural network architectures is carried out using methods that optimize a particular objective function, in which a point that minimizes the function is sought. In reported works, they only focused on software simulations or commercial complementary metal-oxide-semiconductor (CMOS), neither of which guarantees the quality of the solution. In this work, we designed a hardware architecture using individual neurons as building blocks based on the optimization of n-dimensional objective functions, such as obtaining the bias and synaptic weight parameters of an artificial neural network (ANN) model using the gradient descent method. The ANN-based architecture has a 5-3-1 configuration and is implemented on a 1.2 μm technology integrated circuit, with a total power consumption of 46.08 mW, using nine neurons and 36 CMOS operational amplifiers (op-amps). We show the results obtained from the application of integrated circuits for ANNs simulated in PSpice applied to the classification of digital data, demonstrating that the optimization method successfully obtains the synaptic weights and bias values generated by the learning algorithm (Steepest-Descent), for the design of the neural architecture.

Per-Core Power Modeling for Heterogenous SoCs

State-of-the-art mobile platforms, such as smartphones and tablets, are powered by heterogeneous system-on-chips (SoCs). These SoCs are composed of many processing elements, including multiple CPU core clusters (e.g., big.LITTLE cores), graphics processing units (GPUs), memory controllers and other on-chip resources. On the one hand, mobile platforms need to provide a swift response time for interactive apps and high throughput for graphics-oriented workloads; on the other hand, the power consumption must be under tight control to prevent high skin temperatures and energy consumption. Therefore, commercial systems feature a range of mechanisms for dynamic power and temperature control. However, these techniques rely on simple indicators, such as core utilization and total power consumption. System architects are typically limited to the total power consumption, since multiple resources share the same power rail. More importantly, most of the power rails are not exposed to the input/output pins. To address this challenge, this paper presents a thorough methodology to model the power consumption of major resources in heterogeneous SoCs. The proposed models utilize a wide range of performance counters to capture the workload dynamics accurately. Experimental validation on a Nexus 6P phone, powered by an octa-core Snapdragon 810 SoC, showed that the proposed models can estimate the power consumption within a 10% error margin.