Optimization of Hybrid CMOS Designs Using a New Energy Efficient 1 Bit Hybrid Full Adder

2018 ◽  
Author(s):  
S Lakshmi ◽  
C Meenu Raj ◽  
Deepti Krishnadas
Keyword(s):  
Energy Efficient ◽  
Full Adder ◽  
Hybrid Cmos ◽  
New Energy

scholarly journals Design and Implementation of Energy Efficient Power Gated MALFA Cell

2019 ◽  
Vol 8 (4) ◽  
pp. 1178-1181
Keyword(s):  
Power Consumption ◽  
Energy Efficient ◽  
Full Adder ◽  
Power Reduction ◽  
Power Gating ◽  
Hybrid Power ◽  
Reduction Techniques ◽  
Hybrid Cmos ◽  
Adiabatic Logic ◽  
Efficient Power

Power gating is one of the power reduction techniques that is mostly suitable for low power VLSI applications. It reduces the power consumption by shutting of the current to the blocks not in use. Hybrid power gating is applied to Modified Adiabatic Logic based Full Adder (ALFA) cell. The proposed ALFA cell reduces the energy consumption by 67.21%, 51.31%, 55.86% and 27.01% when compared to CMOS FA, PTL with TG 16T, hybrid CMOS and PTL with TG 14T. ALFA cell with hybrid power gating technique reduces the power consumption by 1.76, 2.08%, 1.13%, 1.44%, 0.48% and delay by 5.92%, 11.19%, 11.19%, 5.92%, 24.92% when compared to ALFA cell with NMOS sleepy approach, PMOS sleepy approach, PMOS sleepy stack approach, NMOS sleepy stack approach and dual stack approach.

An Energy Efficient 16T Hybrid-CMOS Full Adder using Novel Full Swing XNOR Logic

2020 ◽  
Author(s):  
Keshav Kumar Mishra ◽  
Avaneesh K. Dubey ◽  
Vikrant Varshney ◽  
Kamal Prakash Pandey
Keyword(s):  
Energy Efficient ◽  
Full Adder ◽  
Hybrid Cmos ◽  
Full Swing

A New Energy-Efficient Hybrid and Clustering Routing for Wireless Sensor Networks

2017 ◽  
Vol 7 (3) ◽  
pp. 176
Author(s):  
Muneer Bani Yassein ◽  
Yaser Khamayseh ◽  
Ismail Hmeidi ◽  
Ahmed Al-Dubai ◽  
Mohammed Al-Maolegi
Keyword(s):  
Wireless Sensor Networks ◽  
Sensor Networks ◽  
Energy Efficient ◽  
Wireless Sensor ◽  
New Energy
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