scholarly journals Design and Implementation of Energy Efficient Power Gated MALFA Cell

2019 ◽  
Vol 8 (4) ◽  
pp. 1178-1181
Keyword(s):  
Power Consumption ◽  
Energy Efficient ◽  
Full Adder ◽  
Power Reduction ◽  
Power Gating ◽  
Hybrid Power ◽  
Reduction Techniques ◽  
Hybrid Cmos ◽  
Adiabatic Logic ◽  
Efficient Power

Power gating is one of the power reduction techniques that is mostly suitable for low power VLSI applications. It reduces the power consumption by shutting of the current to the blocks not in use. Hybrid power gating is applied to Modified Adiabatic Logic based Full Adder (ALFA) cell. The proposed ALFA cell reduces the energy consumption by 67.21%, 51.31%, 55.86% and 27.01% when compared to CMOS FA, PTL with TG 16T, hybrid CMOS and PTL with TG 14T. ALFA cell with hybrid power gating technique reduces the power consumption by 1.76, 2.08%, 1.13%, 1.44%, 0.48% and delay by 5.92%, 11.19%, 11.19%, 5.92%, 24.92% when compared to ALFA cell with NMOS sleepy approach, PMOS sleepy approach, PMOS sleepy stack approach, NMOS sleepy stack approach and dual stack approach.

scholarly journals An Efficient Power Optimized 32 bit BCD Adder Using Multi-Channel Technique

2017 ◽  
Vol 6 (02) ◽  
pp. 07-12
Author(s):  
Diksha Siddhamshittiwar
Keyword(s):  
Average Power ◽  
Full Adder ◽  
Deep Submicron ◽  
Power Reduction ◽  
Vlsi Circuits ◽  
Power Gating ◽  
Static Power ◽  
Simulation Results ◽  
Efficient Power ◽  
Standby Mode

Static power reduction is a challenge in deep submicron VLSI circuits. In this paper 28T full adder circuit, 14T full adder circuit and 32 bit power gated BCD adder using the full adders respectively were designed and their average power was compared. In existing work a conventional full adder is designed using 28T and the same is used to design 32 bit BCD adder. In the proposed architecture 14T transmission gate based power gated full adder is used for the design of 32 bit BCD adder. The leakage supremacy dissipated during standby mode in all deep submicron CMOS devices is reduced using efficient power gating and multi-channel technique. Simulation results were obtained using Tanner EDA and TSMC_180nm library file is used for the design of 28T full adder, 14T full adder and power gated BCD adder and a significant power reduction is achieved in the proposed architecture.

scholarly journals Analysis of CMOS Comparator in 90nm Technology with Different Power Reduction Techniques

2018 ◽  
Vol 8 (6) ◽  
pp. 4922
Author(s):  
Anil Khatak ◽  
Manoj Kumar ◽  
Sanjeev Dhull
Keyword(s):  
Power Consumption ◽  
Leakage Current ◽  
Supply Voltage ◽  
Cmos Technology ◽  
Power Reduction ◽  
Total Power ◽  
Low Power Consumption ◽  
Power Gating ◽  
Reduction Techniques ◽  
Total Power Consumption

To reduce power consumption of regenerative comparator three different techniques are incorporated in this work. These techniques provide a way to achieve low power consumption through their mechanism that alters the operation of the circuit. These techniques are pseudo NMOS, CVSL (cascode voltage switch logic)/DCVS (differential cascode voltage switch) & power gating. Initially regenerative comparator is simulated at 90 nm CMOS technology with 0.7 V supply voltage. Results shows total power consumption of 15.02 μW with considerably large leakage current of 52.03 nA. Further, with pseudo NMOS technique total power consumption increases to 126.53 μW while CVSL shows total power consumption of 18.94 μW with leakage current of 1270.13 nA. More then 90% reduction is attained in total power consumption and leakage current by employing the power gating technique. Moreover, the variations in the power consumption with temperature is also recorded for all three reported techniques where power gating again show optimum variations with least power consumption. Four more conventional comparator circuits are also simulated in 90nm CMOS technology for comparison. Comparison shows better results for regenerative comparator with power gating technique. Simulations are executed by employing SPICE based on 90 nm CMOS technology.

scholarly journals Design of Low Power Multiplier with Energy Efficient Full Adder Using DPTAAL

VLSI Design ◽  
2013 ◽  
Vol 2013 ◽  
pp. 1-9 ◽  
Author(s):  
A. Kishore Kumar ◽  
D. Somasundareswari ◽  
V. Duraisamy ◽  
T. Shunbaga Pradeepa
Keyword(s):  
Low Power ◽  
Energy Efficient ◽  
Full Adder ◽  
Double Pass ◽  
Voltage Level ◽  
Circuit Performance ◽  
Adiabatic Logic ◽  
Pass Transistor ◽  
Cmos Implementation ◽  
Low Power Multiplier

Asynchronous adiabatic logic (AAL) is a novel lowpower design technique which combines the energy saving benefits of asynchronous systems with adiabatic benefits. In this paper, energy efficient full adder using double pass transistor with asynchronous adiabatic logic (DPTAAL) is used to design a low power multiplier. Asynchronous adiabatic circuits are very low power circuits to preserve energy for reuse, which reduces the amount of energy drawn directly from the power supply. In this work, an 8×8 multiplier using DPTAAL is designed and simulated, which exhibits low power and reliable logical operations. To improve the circuit performance at reduced voltage level, double pass transistor logic (DPL) is introduced. The power results of the proposed multiplier design are compared with the conventional CMOS implementation. Simulation results show significant improvement in power for clock rates ranging from 100 MHz to 300 MHz.

scholarly journals Energy Efficient GDI Based Full Adders For Computing Applications

2020 ◽  
Vol 4 (6) ◽  
pp. 5-9
Author(s):  
Bilal N Md ◽  
Bhaskara Rao K ◽  
Mohan Das S
Keyword(s):  
Energy Consumption ◽  
Power Consumption ◽  
Energy Efficient ◽  
Supply Voltage ◽  
Logic Gates ◽  
Full Adder ◽  
Low Power Consumption ◽  
Basic Logic ◽  
Power Delay Product ◽  
Full Swing

This This paper presents energy efficient GDI based 1-bit full adder cells with low power consumption and lesser delay with full swing modified basic logic gates to have reduced Power Delay Product (PDP). The various full adders are effectively realized by means of full swing OR, AND and XOR gates with the noteworthy enhancement in their performance. The simulations for the designed circuits performed in cadence virtuoso tool with 45-nm CMOS technologies at a supply voltage of 1 Volts. The proposed 1-bit adder cells are compared with various basic adders based on speed, power consumption and energy (PDP). The proposed adder schemes with full swing basic cells achieve significant savings in terms of delay and energy consumption and which are more than 41% and 32% respectively in comparison to conventional “C-CMOS” 1-bit full adder and other existing adders.

scholarly journals ROBUST AND SECURE S-BOX DESIGN WITH GATED HYBRID ENERGY RECOVERY LOGIC (GHERL) FOR IOT APPLICATIONS

10.6036/10108 ◽  
2022 ◽  
Vol 97 (1) ◽  
pp. 79-84
Author(s):  
RUBAN GLADWIN ◽  
NEHRU KASTHURI
Keyword(s):  
Internet Of Things ◽  
Power Consumption ◽  
Cyber Security ◽  
Energy Recovery ◽  
High Energy ◽  
Leakage Power ◽  
Handheld Devices ◽  
Power Gating ◽  
Hybrid Energy ◽  
Adiabatic Logic

The smart Internet of Things (IoT) network relies heavily on data transmission over wireless channels. Hence, it should be designed to be robust against the attacks from hackers and antagonists. The confidentiality in IoT devices is directly proportional to the complexity and power consumption. To mitigate these issues, this paper proposes a secure Substitution Box (S-Box) design that is exploited in the IoT for cyber security applications. The S-Box is based on Gated Hybrid Energy Recovery Logic (GHERL) that is an amalgamation of two different techniques as adiabatic logic and power gating. Adiabatic logic is preferred to attain high energy efficiency in practical applications such as portable and handheld devices. Power gating technique is preferred to reduce the leakage power and energy consumption. The proposed GHERL XOR gate and S-Box are implemented with 125nm technology in Tanner EDA tool. The consequences of the experiments exhibits that the novel S-Box design with GHERL XOR decreases the power consumption by 1.76%, 35.26%, 36.81%, 41.01% and reduces the leakage power by 58.54%, 20.27%, 27.38%, 13.63% when compared with the existing techniques such as S-Box with sleep transistor, dual sleep transistor, dual-stack and sleepy keeper approach. Keywords: Adiabatic logic, Power Gating, Internet of Things, S-Box

Nonvolatile Power-Gating FPGA Based on Pseudo-Spin-Transistor Architecture with Spin-Transfer-Torque MTJs

2012 ◽  
Vol 1430 ◽  
Author(s):  
Shuu’ichirou Yamamoto ◽  
Yusuke Shuto ◽  
Satoshi Sugahara
Keyword(s):  
Nonvolatile Memory ◽  
Spin Transfer Torque ◽  
Spin Transfer ◽  
Power Gating ◽  
Reduction Techniques ◽  
Logic Block ◽  
Field Programmable ◽  
Spin Transistor ◽  
Efficient Power ◽  
Circuit Configuration

ABSTRACTWe proposed and computationally analyzed a nonvolatile power-gating field programmable gate array (NVPG-FPGA) based on pseudo-spin-transistor architecture with spin-transfer-torque magnetic tunnel junctions (STT-MTJs). The circuit employs nonvolatile static random memory (NV-SRAM) cells and nonvolatile flip-flops (NV-FFs) as the storage circuits. The circuit configuration and microarchitecture are compatible with SRAM-based FPGAs, and the additional nonvolatile memory functionality makes it possible to execute efficient power-gating (PG). Break-even time (BET) for the nonvolatile configuration logic block (NV-CLB) of the NVPG-FPGA was also analyzed, and reduction techniques of the BET were proposed, which allows highly efficient PG operations with a fine granularity.

scholarly journals Design of Low Power Adders in Digital Circuits Suitable for Power Reduction in Multipliers

2020 ◽  
Vol 9 (3) ◽  
pp. 1657-1662
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Digital Circuits ◽  
Evolutionary Process ◽  
Full Adder ◽  
Power Reduction ◽  
Wireless Devices ◽  
Xor Gate ◽  
Core Areas ◽  
Static Energy

Wireless devices are being evolved at an exponential rate. This evolution is focussing on the development of digital circuits which are incorporated into the processors. The evolutionary process involves individually or a combination of three main objectives namely i) Reduction in size ii) Reduction in power iii) Increase in speed. There is always a trade-off among the above said objectives. In specific multiplying operation inside a processor is one of the core areas where much power is being consumed. On the other hand adders are an integral part in the multiplier circuit. So this work concentrates on designing and analyzing power consumption of five adders namely conventional full adder, 3-transistor XOR based full adder, Gate Diffusion Input (GDI) based full adder, Static Energy Recovery Full (SERF) Adder and full adder using modified XOR gate and finding a resultant low power adder which when implemented for the addition process in multiplier will lead to a reduction in power consumption of multiplier. This in turn reduce the overall power consumption of the processor. The adders are designed using LTSPICE XVII in 180nm technology. The resultant Full Adder using modified XOR gate achieves 61.79% less power compared to conventional full adder and is suitable for multipliers.

scholarly journals Design and Analysis of Low Power Dual Edge Triggered Mechanism Flip-Flop Employing Power Gating Methodology

2020 ◽  
Vol 6 (01) ◽  
pp. 26-31
Author(s):  
Prof. Virendra Umale
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Reduction Technique ◽  
Power Gating ◽  
Flip Flop ◽  
Ultra Low Power ◽  
Efficient Power

The advancement of battery operated designs has abundantly increases the memory elements and registers to be operated in ultra-low power. That is the this paper we have proposed a design of CT_C DET flip-flop with power gating technique which is the most efficient power consuming reduction technique.  The design of the power gating technique involves the pull-up transistor in the Vdd of the circuit and pull-down transistor in the ground terminal. This power gating technique reduces the power consumption by more than 40% than that of the existing design.

Sign in / Sign up

Export Citation Format

Share Document