A noise-tolerant dynamic circuit design technique

Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044) ◽

10.1109/cicc.2000.852700 ◽

2002 ◽

Author(s):

G. Balamurugan ◽

N.R. Shanbhag

Keyword(s):

Circuit Design ◽

Design Technique ◽

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Novel low power noise tolerant dynamic circuit design technique

TENCON 2009 - 2009 IEEE Region 10 Conference ◽

10.1109/tencon.2009.5396245 ◽

2009 ◽

Author(s):

Kaushik Mazumdar ◽

Manisha Pattanaik ◽

R. Bhanu Prakash

Keyword(s):

Low Power ◽

Circuit Design ◽

Design Technique ◽

Power Noise ◽

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Analog integrated Circuit Design Technique Can be applied to Many Other Purposes besides LSI.

The Journal of the Institute of Electrical Engineers of Japan ◽

10.1541/ieejjournal.134.283 ◽

2014 ◽

Vol 134 (5) ◽

pp. 283-283

Author(s):

Daisuke KANEMOTO

Keyword(s):

Circuit Design ◽

Integrated Circuit ◽

Design Technique ◽

Integrated Circuit Design ◽

Analog Integrated Circuit ◽

Analog Integrated Circuit Design

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Radiation Effects on a Small DC-DC Converter and a Remedy by Circuit Design Technique

10.21236/ada403299 ◽

2002 ◽

Author(s):

C. H. Truong ◽

E. J. Simburger ◽

R. C. Lacoe ◽

J. C. Ross ◽

S. Brown

Keyword(s):

Circuit Design ◽

Radiation Effects ◽

Design Technique

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A 0.13μm hardware-efficient probabilistic-based noise-tolerant circuit design and implementation with 24.5dB noise-immunity improvement

2007 IEEE Asian Solid-State Circuits Conference ◽

10.1109/asscc.2007.4425694 ◽

2007 ◽

Author(s):

I-Chyn Wey ◽

You-Gang Chen ◽

Changhong Yu ◽

Jie Chen ◽

An-Yeu Wu

Keyword(s):

Circuit Design ◽

Noise Immunity ◽

Design And Implementation ◽

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A LOW POWER PUSH-PUSH DIFFERENTIAL VCO USING CURRENT-REUSE CIRCUIT DESIGN TECHNIQUE

Progress In Electromagnetics Research C ◽

10.2528/pierc11101806 ◽

2012 ◽

Vol 27 ◽

pp. 85-97 ◽

Author(s):

Sheng-Lyang Jang ◽

Do Anh Tu ◽

Chia-Wei Chang ◽

Miin-Horng Juang

Keyword(s):

Low Power ◽

Circuit Design ◽

Design Technique ◽

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A high-speed CMOS full-adder cell using a new circuit design technique-adaptively-biased pseudo-NMOS logic

10.1109/iscas.1990.112118 ◽

2002 ◽

Author(s):

F. Lu ◽

H. Samueli

Keyword(s):

Circuit Design ◽

Design Technique

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A Novel Low Power Noise Tolerant High Performance Dynamic Feed through Logic Design Technique

2011 International Symposium on Electronic System Design ◽

10.1109/ised.2011.59 ◽

2011 ◽

Author(s):

Manisha Pattanaik ◽

Shashank Parashar ◽

Chaudhry Indra Kumar ◽

Akanksha Chouhan ◽

Vikas Mahor

Keyword(s):

Low Power ◽

High Performance ◽

Logic Design ◽

Design Technique ◽

Power Noise ◽

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A New Noise-Tolerant Dynamic Circuit Design with Enhanced PDP Performance under Low SNR Environment

2006 IEEE Asian Solid-State Circuits Conference ◽

10.1109/asscc.2006.357909 ◽

2006 ◽

Author(s):

You-Gang Chen ◽

I-Chyn Wey ◽

An-Yeu Wu

Keyword(s):

Circuit Design ◽

Low Snr ◽

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A combination of wave-pipelining timing methodology and DPTL circuit design technique

1997 21st International Conference on Microelectronics. Proceedings ◽

10.1109/icmel.1997.632964 ◽

2002 ◽

Author(s):

P. Markovic ◽

D.V. Simic

Keyword(s):

Circuit Design ◽

Design Technique ◽

Wave Pipelining

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A 1.8-V operation 5-GHz-band CMOS frequency doubler using current-reuse circuit design technique

IEEE Journal of Solid-State Circuits ◽

10.1109/jssc.2005.848033 ◽

2005 ◽

Vol 40 (6) ◽

pp. 1288-1295 ◽

Author(s):

K. Yamamoto

Keyword(s):

Circuit Design ◽

Frequency Doubler ◽

Design Technique ◽

Current Reuse ◽

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