A 14-bit 500-MS/s SHA-less Pipelined ADC in 65nm CMOS Technology for Wireless Receiver

Abstract A wideband down conversion ring mixer is proposed for multi band orthogonal frequency division multiplexing (MB-OFDM) system in 180 nm CMOS technology. The mixer is essentially used in a heterodyne wireless receiver to enhance the selectivity of the system. Being a nonlinear system, the mixer dominates the overall performance of the system. The design of down conversion mixer is the most challenging part of a receive chain. Wideband impedance matching always remains a challenge in any radio frequency integrated circuit design. This paper presents the design of a ring mixer with high linearity, wideband impedance matching using differential resistive impedance matching and without using any DC bias. The proposed mixer is tuned for a frequency of 3.432 GHz of band 1 of the MB-OFDM system. Mixer core is based on the FET ring mixer topology. The mixer is implemented in 180 nm CMOS technology. The mixer achieves the minimum conversion loss of 10.49 dB, 1 dB compression point (P1) of 12.40 dBm, third order input intercept point (IIP3) of 12.01 dBm, a minimum SSB noise figure of 8.99 dB, and S 11 of less than -10 dB over the frequency range of 0 to 13.61 GHz . The layout of the mixer records an active area of 183.75 μm 2 .

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A Low-Voltage Low-Power Opamp-Less 8-bit 1-MS/s Pipelined ADC in 90-nm CMOS Technology

IEIE Transactions on Smart Processing and Computing ◽

10.5573/ieiespc.2014.3.6.416 ◽

2014 ◽

Vol 3 (6) ◽

pp. 416-424

Author(s):

Hamed Abbasizadeh ◽

Behnam Samadpoor Rikan ◽

Dong-Soo Lee ◽

Abbas Syed Hayder ◽

Kang-Yoon Lee

Keyword(s):

Low Power ◽

Low Voltage ◽

Cmos Technology ◽

Pipelined Adc

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A 10-b 100-MS/s pipelined ADC with an optimized bit-stage resolution in 65nm CMOS technology

Proceedings of 2010 IEEE International Symposium on Circuits and Systems ◽

10.1109/iscas.2010.5537644 ◽

2010 ◽

Cited By ~ 2

Author(s):

P. Delizia ◽

G. Saccomanno ◽

S. D'Amico ◽

A. Baschirotto

Keyword(s):

Cmos Technology ◽

Pipelined Adc

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Design of A 7-bit, 200MS/s, 2mW pipelined ADC with switched open-loop amplifiers in a 65nm CMOS technology

Norchip 2007 ◽

10.1109/norchp.2007.4481042 ◽

2007 ◽

Cited By ~ 3

Author(s):

Carsten Wulff ◽

Trond Ytterdal

Keyword(s):

Cmos Technology ◽

Open Loop ◽

Pipelined Adc

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Design a 10-Bit 100MHz pipelined ADC using RB-OTA in 90nm CMOS technology

IEICE Electronics Express ◽

10.1587/elex.9.815 ◽

2012 ◽

Vol 9 (8) ◽

pp. 815-821

Author(s):

S. Hassan Mirhosseini ◽

Ahmad Ayatollahi

Keyword(s):

Cmos Technology ◽

Pipelined Adc

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A Reconfiguration Method to Improve the Yield of Bandwidth-Limited Pipelined ADCs

International Journal on Measurement Technologies and Instrumentation Engineering ◽

10.4018/ijmtie.2012010101 ◽

2012 ◽

Vol 2 (1) ◽

pp. 1-16

Author(s):

David Camarero ◽

Manal Lagziri ◽

Kay Suenaga ◽

Rodrigo Picos ◽

Eugeni Garcia-Moreno

Keyword(s):

Monte Carlo ◽

Cmos Technology ◽

Point Of View ◽

Second Step ◽

Pipelined Adc ◽

Op Amps ◽

Front End ◽

Pipelined Adcs ◽

Alternate Test ◽

End Stage

An off-line reconfiguration method is proposed for pipelined ADCs to improve their fabrication yield. Some nonlinearities generated by op amps in pipelined ADC stages depend on their bandwidth, while their equivalent input-referred errors depend on the stage position. From these premises, the method is conceived as a two steps process. During the first step, an alternate-test based technique determines the best stage, from the bandwidth point of view, as the front-end stage. In the second step, analog residue path interconnections and a stage scaling are configured according to the results from the first step. This method has been verified for a 10-bits ADC, designed in a 65 nm CMOS technology, by means of Monte Carlo simulations, with promising results.

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