xB+-Tree: Access-Pattern-Aware Cache-Line-Based Tree for Non-volatile Main Memory Architecture

2017 ◽  
Author(s):  
Li-Zheng Liang ◽  
Ming-Chang Yang ◽  
Yuan-Hao Chang ◽  
Tseng-Yi Chen ◽  
Shuo-Han Chen ◽  
...  
Keyword(s):  
Main Memory ◽  
Memory Architecture ◽  
Access Pattern ◽  
Cache Line

Network Main Memory Architecture for NoC-Based Chips

2010 ◽  
Author(s):  
Xingsheng Tang ◽  
Binbin Wu ◽  
Tianzhou Chen ◽  
Wei Hu ◽  
Jiexiang Kang ◽  
...  
Keyword(s):  
Main Memory ◽  
Memory Architecture

scholarly journals Fine-Grained Data Management for DRAM/SSD Hybrid Main Memory Architecture

2016 ◽  
Vol E99.D (12) ◽  
pp. 3172-3176 ◽  
Author(s):  
Liyu WANG ◽  
Qiang WANG ◽  
Lan CHEN ◽  
Xiaoran HAO
Keyword(s):  
Data Management ◽  
Main Memory ◽  
Memory Architecture ◽  
Fine Grained

Algorithm-Switching-Based Last-Level Cache Structure with Hybrid Main Memory Architecture

2019 ◽  
Author(s):  
Xian-Shu Li ◽  
Su-Kyung Yoon ◽  
Jeong-Geun Kim ◽  
Bernd Burgstaller ◽  
Shin-Dug Kim
Keyword(s):  
Main Memory ◽  
Memory Architecture

scholarly journals Fast and Accurate Memory Simulation by Integrating DRAMSim2 into McSimA+

Electronics ◽  
2018 ◽  
Vol 7 (8) ◽  
pp. 152 ◽  
Author(s):  
Konstantin Bick ◽  
Duy Nguyen ◽  
Hyuk-Jae Lee ◽  
Hyun Kim
Keyword(s):  
Computer Architecture ◽  
System Performance ◽  
High Speed ◽  
High Accuracy ◽  
Main Memory ◽  
Power Model ◽  
Entire System ◽  
Memory Architecture ◽  
Event Driven ◽  
Efficient Integration

Computer architecture simulators play a crucial role in the verification of a new system’s design. However, a single simulator may not be sufficient in covering detailed modeling of the entire system, thereby lacking in the simulation of a specific functionality under investigation. In this case, combining two simulators is necessary to compensate for the drawbacks of a single simulator. This paper proposes the integration of DRAMSim2, a simulator that thoroughly models DDR-SDRAM main memory architecture, into the application-level+ simulator McSimA+. The challenges of achieving an efficient integration, especially the integration of a cycle-accurate simulator into an event-driven environment, are addressed. The combined simulator achieves high accuracy due to cycle-accurate simulation while maintaining high speed and flexibility of the event-driven application-level+ simulator. The new simulator’s overall system performance and the accuracy of the newly-integrated power model are verified against the gem5 simulator.

Self-learnable Cluster-based Prefetching Method for DRAM-Flash Hybrid Main Memory Architecture

2019 ◽  
Vol 15 (1) ◽  
pp. 1-21
Author(s):  
Su-Kyung Yoon ◽  
Young-Sun Youn ◽  
Bernd Burgstaller ◽  
Shin-Dug Kim
Keyword(s):  
Main Memory ◽  
Memory Architecture

scholarly journals TA-CLOCK: Tendency-Aware Page Replacement Policy for Hybrid Main Memory in High-Performance Embedded Systems

Electronics ◽  
2021 ◽  
Vol 10 (9) ◽  
pp. 1111
Author(s):  
Jun Hyeong Choi ◽  
Kyung Min Kim ◽  
Jong Wook Kwak
Keyword(s):  
Embedded Systems ◽  
High Performance ◽  
Pattern Analysis ◽  
Main Memory ◽  
Replacement Policy ◽  
Low Power Consumption ◽  
Access Pattern ◽  
Write Endurance ◽  
Change Memory

Recently, high-performance embedded systems have adopted phase change memory (PCM) as their main memory because PCMs have attractive advantages, such as non-volatility, byte-addressability, high density, and low power consumption. However, PCMs have disadvantages, such as limited write endurance in each cell and high write latency compared to DRAMs. Therefore, researchers have investigated methods for enhancing the limitations of PCMs. In this paper, we propose a page replacement policy called tendency-aware CLOCK (TA-CLOCK) for the hybrid main memory of embedded systems. To improve the limited write endurance of PCMs, TA-CLOCK classifies the page access tendency of the victim page through access pattern analysis and determines the migration location of the victim page. Through the classification of the page access tendency, TA-CLOCK reduces unnecessary page migrations from DRAMs to PCMs. Unnecessary migrations cause an increase in write operations in PCMs and the energy consumption of the hybrid main memory in embedded systems. Thus, our proposed policy improves the limited write endurance of PCMs and enhances the access latency of the hybrid main memory of embedded systems by classifying the page access tendency. We compared the TA-CLOCK with existing page replacement policies to evaluate its performance. In our experiments, TA-CLOCK reduced the number of write operations in PCMs by 71.5% on average, and it enhanced the energy delay product by 38.3% on average compared with other page replacement policies.

scholarly journals Cache Coherence Protocol Design and Simulation Using IES (Invalid Exclusive read/write Shared) State

2017 ◽  
Vol 14 (1) ◽  
pp. 219-230
Author(s):  
Baghdad Science Journal
Keyword(s):  
Cache Coherence ◽  
Main Memory ◽  
Protocol Design ◽  
Memory Architecture ◽  
Cache Memories ◽  
Cache Coherence Protocol ◽  
Cache Coherency ◽  
Processor Efficiency ◽  
Shared State ◽  
Access Data

To improve the efficiency of a processor in recent multiprocessor systems to deal with data, cache memories are used to access data instead of main memory which reduces the latency of delay time. In such systems, when installing different caches in different processors in shared memory architecture, the difficulties appear when there is a need to maintain consistency between the cache memories of different processors. So, cache coherency protocol is very important in such kinds of system. MSI, MESI, MOSI, MOESI, etc. are the famous protocols to solve cache coherency problem. We have proposed in this research integrating two states of MESI's cache coherence protocol which are Exclusive and Modified, which responds to a request from reading and writing at the same time and that are exclusive to these requests. Also back to the main memory from one of the other processor that has a modified state is removed in using a proposed protocol when it is invalidated as a result of writing to that location that has the same address because in all cases it depends on the latest value written and if back to memory is used to protect data from loss; preprocessing steps to IES protocol is used to maintain and saving data in main memory when it evict from the cache. All of this leads to increased processor efficiency by reducing access to main memory

Sign in / Sign up

Export Citation Format

Share Document