Processor performance metrics analysis and implementation for MIPS using an open source OS

<p><span>Processor efficiency is a important in embedded system. The efficiency of the processor depends on the L1 cache and translation lookaside buffer (TLB). It is required to understand the L1 cache and TLB performances during varied load for the execution on the processor and hence studies the performance of the varing load and its performance with caches with MIPS and operating system (OS) are studied in this paper. The proposed methods of implementation in the paper considers the counting of the instruction exxecution for respective cache and TLB management and the events are measured using a dedicated counters in software. The software counters are used as there are limitation to hardware counters in the MIPS32. Twenty-seven metrics are considered for analysis and proper identification and implemented for the performance measurement of L1 cache and TLB on the MIPS32 processor. The generated data helps in future research in compiler tuning, memory management design for OS, analysing architectural issues, system benchmarking, scalability, address space analysis, studies of bus communication among processor and its workload sharing characterisation and kernel profiling.</span></p>

DIFFERENCES IN THE STRUCTURE OF COGNITIVE ABILITIES BETWEEN FEMALE AND MALE STUDENTS OF THE HIGH SCHOOL IN ARILJE

Cognitive (intellectual) processes are, on the basis of Plato's psychological trinoma (cognition - affection - connection), the most intensively studied processes in psychology. Intelligence, as the center of these processes, despite serious efforts, remained insufficiently known. The proof of this statement is the existence of numerous conceptions about the types of cognitive functioning.Cognitive abilities were measured in the first lessons,the presence of psychologists, subject teachers and authors of this research. All of the administered tests are essentially speed tests, so respondents do not have time to contact and communicate with other respondents. A battery of KOG-3 tests was used to assess cognitive ability (Wolf, Momirović, and Džamonja 1992).The KOG-3 battery is the minimum battery for evaluating the performance of a perceptual, serial, and parallel processor. The version of that battery was used to achieve the basic goal, ie. to determine the level of general cognitive ability. The battery consists of three tests:Image Comparison Test (IT1), the basic version was designed by Thurstone. The test is designed as a test of the general perceptual factor, which is in fact a synthesis of primary factors of perceptual identification, perceptual analysis and perceptual structuring. The completiontime is limited to 4 minutes.Synonym test (AL4), the basic version was designed by Wels. The test is constructed as a test of verbal comprehension. The completiontime is limited to 2 minutes andVisual Specialization Test(S1), the basic version was designed by Reuchlin and Valin. The test is designed as a classical multiple choice special test. The completiontime is limited to 8 minutes.The aim of this research is to identify and determine the specificity of the cognitive abilities of latent dimensions, as well as their differences, between female and male students in relation to gender.On the basis of the formulated problem, the subject matter and the established general and partial goals, the basic alternative hypothesis was put forward:H2. The structure of female and male students' cognitive abilities will provide unambiguous evidence thatis of hierarchical type, with thegeneral cognitive factor at the top, below which are the three primary cognitive factors, defined as:efficiency of perceptual processor (perceptual reasoning), IT-1; parallel processor efficiency (ability to spot, relate, and correlate), SI-1, and serial processor efficiency (symbolic reasoning). AL-4.H5 - No statistically significant differences in the analyzed cognitive abilities are expected between students of different gender and age.

Evaluation of Strategies for the Development of Efficient Code for Raspberry Pi Devices

The Internet of Things (IoT) is faced with challenges that require green solutions and energy-efficient paradigms. Architectures (such as ARM) have evolved significantly in recent years, with improvements to processor efficiency, essential for always-on devices, as a focal point. However, as far as software is concerned, few approaches analyse the advantages of writing efficient code when programming IoT devices. Therefore, this proposal aims to improve source code optimization to achieve better execution times. In addition, the importance of various techniques for writing efficient code for Raspberry Pi devices is analysed, with the objective of increasing execution speed. A complete set of tests have been developed exclusively for analysing and measuring the improvements achieved when applying each of these techniques. This will raise awareness of the significant impact the recommended techniques can have.

Parallel Processor Architecture with a New Algorithm for Simultaneous Processing of MIPS-Based Series Instructions

Processors are main part of the calculation and decision making of a system. Today, due to the increasing need of industry and technology to faster and more accurate computing power, design and manufacture of parallel processing units, has been very much considered. One of the most important processor families used in various devises is the MIPS processors. This processor family had been considered in the telecom and control industry as a reasonable choice. In this paper, new architecture based on this processor, with new parallel processing design, is provided to allow parallel execution of instructions dynamically. Ultimately, the processor efficiency to several fold will be increased. In this architecture, new ideas for the issuance of instructions in parallel, intelligent detection of conditional jumps and memory management are presented.

Cache coherence protocol design using VMSI (Valid Modified Shared Invalid) states

We have proposed in this research the design of a new protocol named VMSI coherence protocol in the cache in order to solve the problem of coherence which is the incompatibility of data between caches that appeared in recent multiprocessors system through the operations of reading and writing. The main purpose of this protocol is to increase processor efficiency by reducing traffic between processor and memory that have been achieved through the removal of the write back to the main memory in the case of reading or writing of shared caches because it depends on existing directory inside that cache which contains all the data that represents a subset of main memory.

Cache Coherence Protocol Design and Simulation Using IES (Invalid Exclusive read/write Shared) State

To improve the efficiency of a processor in recent multiprocessor systems to deal with data, cache memories are used to access data instead of main memory which reduces the latency of delay time. In such systems, when installing different caches in different processors in shared memory architecture, the difficulties appear when there is a need to maintain consistency between the cache memories of different processors. So, cache coherency protocol is very important in such kinds of system. MSI, MESI, MOSI, MOESI, etc. are the famous protocols to solve cache coherency problem. We have proposed in this research integrating two states of MESI's cache coherence protocol which are Exclusive and Modified, which responds to a request from reading and writing at the same time and that are exclusive to these requests. Also back to the main memory from one of the other processor that has a modified state is removed in using a proposed protocol when it is invalidated as a result of writing to that location that has the same address because in all cases it depends on the latest value written and if back to memory is used to protect data from loss; preprocessing steps to IES protocol is used to maintain and saving data in main memory when it evict from the cache. All of this leads to increased processor efficiency by reducing access to main memory

Hyper Threading Technology in Hardware Architecture for Processor Efficiency Enhancement

Intel’s Hyper-Threading Technology brings the concept of simultaneous multi-threading to the Intel architecture. Hyper-Threading Technology makes a single physical processor appear as two logical processors; the physical execution resources are shared and the architecture state is duplicated for the two logical processors. From a software or architecture perspective, this means operating systems and user programs can schedule processes or threads to logical processors as they would on multiple physical processors. From a micro architecture perspective, this means that instructions from both logical processors will persist and execute simultaneously on shared execution resources. This paper describes the Hyper-Threading Technology architecture of Intel’s first implementation on the Intel Xeon processor family. Hyper-Threading Technology is an important addition to Intel’s enterprise product line and will be integrated into a wide variety of products.