Analyzing cycle stealing on synchronous circuits with level-sensitive latches

2003 ◽  
Author(s):  
I. Lin ◽  
J.A. Ludwig ◽  
K. Eng
Keyword(s):  
Synchronous Circuits ◽  
Cycle Stealing

scholarly journals An Initialization Technique for the Waveform-Relaxation Circuit Simulation

VLSI Design ◽  
1999 ◽  
Vol 9 (2) ◽  
pp. 213-218 ◽  
Author(s):  
S. E.-D. Habib ◽  
G. J. Al-Karim
Keyword(s):  
Circuit Simulation ◽  
Waveform Relaxation ◽  
Synchronous Circuits ◽  
Highly Effective ◽  
Initialization Scheme

This paper reports the development of the Cairo University Waveform Relaxation (CUWORX) simulator. In order to accelerate the convergence of the waveform relaxation (WR) in the presence of logic feedback, CUWORK is initialized via a logic simulator. This logic initialization scheme is shown to be highly effective for digital synchronous circuits. Additionally, this logic initialization scheme preserves fully the multi-rate properties of the WR algorithm.

scholarly journals FAILURE TOLERANT SYNCHRONOUS AND SELT-TIED CIRCUITS COMPARISON

2021 ◽  
Author(s):  
Aleksandr Zatsarinny ◽  
Yuri Stepchenkov ◽  
Yuri Diachenko ◽  
Yuri Rogdestvenski
Keyword(s):  
Digital Circuits ◽  
Soft Error ◽  
Error Tolerance ◽  
Electronic Circuits ◽  
Two Phase ◽  
Synchronous Circuits ◽  
Tolerance Level ◽  
Failure Tolerance ◽  
Hardware Costs ◽  
Signal Coding

The article considers the problem of developing synchronous and self-timed (ST) digital circuits that are tolerant to soft errors. Synchronous circuits traditionally use the 2-of-3 voting principle to ensure single failure, resulting in three times the hardware costs. In ST circuits, due to dual-rail signal coding and two-phase control, even duplication provides a soft error tolerance level 2.1 to 3.5 times higher than the triple modular redundant synchronous counterpart. The development of new high-precision software simulating microelectronic failure mechanisms will provide more accurate estimates for the electronic circuits' failure tolerance

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