scholarly journals FAILURE TOLERANT SYNCHRONOUS AND SELT-TIED CIRCUITS COMPARISON

2021 ◽  
Author(s):  
Aleksandr Zatsarinny ◽  
Yuri Stepchenkov ◽  
Yuri Diachenko ◽  
Yuri Rogdestvenski
Keyword(s):  
Digital Circuits ◽  
Soft Error ◽  
Error Tolerance ◽  
Electronic Circuits ◽  
Two Phase ◽  
Synchronous Circuits ◽  
Tolerance Level ◽  
Failure Tolerance ◽  
Hardware Costs ◽  
Signal Coding

The article considers the problem of developing synchronous and self-timed (ST) digital circuits that are tolerant to soft errors. Synchronous circuits traditionally use the 2-of-3 voting principle to ensure single failure, resulting in three times the hardware costs. In ST circuits, due to dual-rail signal coding and two-phase control, even duplication provides a soft error tolerance level 2.1 to 3.5 times higher than the triple modular redundant synchronous counterpart. The development of new high-precision software simulating microelectronic failure mechanisms will provide more accurate estimates for the electronic circuits' failure tolerance

scholarly journals Categorization and SEU Fault Simulations of Radiation-Hardened-by-Design Flip-Flops

Electronics ◽  
2021 ◽  
Vol 10 (13) ◽  
pp. 1572
Author(s):  
Ehab A. Hamed ◽  
Inhee Lee
Keyword(s):  
Soft Error ◽  
Error Tolerance ◽  
Cmos Process ◽  
Flip Flop ◽  
Single Event Upsets ◽  
Area Overhead ◽  
Fair Comparison ◽  
Reference Design ◽  
Radiation Hardened ◽  
Radiation Hardened By Design

In the previous three decades, many Radiation-Hardened-by-Design (RHBD) Flip-Flops (FFs) have been designed and improved to be immune to Single Event Upsets (SEUs). Their specifications are enhanced regarding soft error tolerance, area overhead, power consumption, and delay. In this review, previously presented RHBD FFs are classified into three categories with an overview of each category. Six well-known RHBD FFs architectures are simulated using a 180 nm CMOS process to show a fair comparison between them while the conventional Transmission Gate Flip-Flop (TGFF) is used as a reference design for this comparison. The results of the comparison are analyzed to give some important highlights about each design.

Evaluation of Soft-Error Tolerance by Neutrons and Heavy Ions on Flip Flops With Guard Gates in a 65-nm Thin BOX FDSOI Process

2020 ◽  
Vol 67 (7) ◽  
pp. 1470-1477
Author(s):  
Mitsunori Ebara ◽  
Kodai Yamada ◽  
Kentaro Kojima ◽  
Yuto Tsukita ◽  
Jun Furuta ◽  
...  
Keyword(s):  
Heavy Ions ◽  
Soft Error ◽  
Error Tolerance
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