Multiphase synchronous circuits for low power performance

1998 ◽  
Vol 29 (3) ◽  
pp. 105-111
Author(s):  
R. Andrew ◽  
K. Venos
Keyword(s):  
Low Power ◽  
Power Performance ◽  
Synchronous Circuits

scholarly journals Rapid Liquid Fuel Mixing for Lean-Burning Combustors: Low-Power Performance

2001 ◽  
Vol 123 (3) ◽  
pp. 574-579 ◽  
Author(s):  
M. Y. Leong ◽  
C. S. Smugeresky ◽  
V. G. McDonell ◽  
G. S. Samuelsen
Keyword(s):  
Low Power ◽  
Gas Turbine ◽  
Liquid Fuel ◽  
Direct Injection ◽  
Fuel Injector ◽  
Power Performance ◽  
Lean Burn ◽  
Engine Operation ◽  
Turbine Engine ◽  
Lean Direct Injection

Designers of advanced gas turbine combustors are considering lean direct injection strategies to achieve low NOx emission levels. In the present study, the performance of a multipoint radial airblast fuel injector Lean Burn injector (LBI) is explored for various conditions that target low-power gas turbine engine operation. Reacting tests were conducted in a model can combustor at 4 and 6.6 atm, and at a dome air preheat temperature of 533 K, using Jet-A as the liquid fuel. Emissions measurements were made at equivalence ratios between 0.37 and 0.65. The pressure drop across the airblast injector holes was maintained at 3 and 7–8 percent. The results indicate that the LBI performance for the conditions considered is not sufficiently predicted by existing emissions correlations. In addition, NOx performance is impacted by atomizing air flows, suggesting that droplet size is critical even at the expense of penetration to the wall opposite the injector. The results provide a baseline from which to optimize the performance of the LBI for low-power operation.

scholarly journals Rapid Liquid Fuel Mixing for Lean-Burning Combustors: Low-Power Performance

2000 ◽  
Author(s):  
May Y. Leong ◽  
Craig S. Smugeresky ◽  
Vincent G. McDonell ◽  
G. Scott Samuelsen
Keyword(s):  
Low Power ◽  
Gas Turbine ◽  
Liquid Fuel ◽  
Direct Injection ◽  
Fuel Injector ◽  
Power Performance ◽  
Lean Burn ◽  
Engine Operation ◽  
Turbine Engine ◽  
Lean Direct Injection

Designers of advanced gas turbine combustors are considering lean direct injection strategies to achieve low NOx emission levels. In the present study, the performance of a multipoint radial airblast fuel injector (“Lean Burn Injector—LBI”) is explored for various conditions that target low-power gas turbine engine operation. Reacting tests were conducted in a model can combustor at 4 atm and 6.6 atm, and at a dome air preheat temperature of 533 K, using Jet-A as the liquid fuel. Emissions measurements were made at equivalence ratios between 0.37 and 0.65. The pressure drop across the airblast injector holes was maintained at 3% and 7–8%. The results indicate that the LBI performance for the conditions considered is not sufficiently predicted by existing emissions correlations. In addition, NOx performance is impacted by atomizing air flows, suggesting that droplet size is critical even at the expense of penetration to the wall opposite the injector. The results provide a baseline from which to optimize the performance of the LBI for low-power operation.

scholarly journals A 0.3 V PNN Based 10T SRAM with Pulse Control Based Read-Assist and Write Data-Aware Schemes for Low Power Applications

Sensors ◽  
2021 ◽  
Vol 21 (19) ◽  
pp. 6591
Author(s):  
Ming-Hwa Sheu ◽  
Chang-Ming Tsai ◽  
Ming-Yan Tsai ◽  
Shih-Chang Hsia ◽  
S. M. Salahuddin Morsalin ◽  
...  
Keyword(s):  
Low Power ◽  
Supply Voltage ◽  
Random Access ◽  
Average Energy ◽  
Cmos Process ◽  
Pulse Control ◽  
Power Performance ◽  
Process Technology ◽  
Low Leakage ◽  
Noise Margin

An innovative and stable PNN based 10-transistor (10T) static random-access memory (SRAM) architecture has been designed for low-power bit-cell operation and sub-threshold voltage applications. The proposed design belongs to the following features: (a) pulse control based read-assist circuit offers a dynamic read decoupling approach for eliminating the read interference; (b) we have utilized the write data-aware techniques to cut off the pull-down path; and (c) additional write current has enhanced the write capability during the operation. The proposed design not only solves the half-selected problems and increases the read static noise margin (RSNM) but also provides low leakage power performance. The designed architecture of 1-Kb SRAM macros (32 rows × 32 columns) has been implemented based on the TSMC-40 nm GP CMOS process technology. At 300 mV supply voltage and 10 MHz operating frequency, the read and write power consumption is 4.15 μW and 3.82 μW, while the average energy consumption is only 0.39 pJ.

A Novel Darlington-Based 8T CNTFET SRAM Cell for Low Power Applications

2021 ◽  
pp. 2150213
Author(s):  
M. Elangovan
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Simulation Tool ◽  
Stanford University ◽  
Memory Cells ◽  
Power Performance ◽  
Dynamic Power ◽  
Memory Design ◽  
Noise Margin ◽  
Sram Cell

The design of low power memory cells is the dream of engineers in memory design. A Darlington-based 8T CNTFET SRAM cell is suggested in this paper. It is called the proposed P_CNTFET Darlington 8T SRAM Cell. Compared with that of the traditional 6T and 8T CNTFET SRAM cells, the power and noise performances of the proposed SRAM cell are comparable. Compared to the traditional SRAM cells, the write, hold, read and dynamic power consumption of the proposed cell is much lower. The CNTFET parameters are optimized to boost the noise margin performance of the suggested bit cell. For optimized parameters, the power consumption and SNM of the proposed cell are compared with conventional cells. In contrast to the conventional cells, the HSNM and WSNM of the proposed cell are improved by 6.25% and 66.6%. The proposed cell’s RSNM is 38% greater than the traditional 6T SRAM cell. The proposed cell’s RSNM is 3.33% less than the traditional 8T SRAM cell. MOSFET is also used to implement the proposed SRAM cell and its noise margin and power performance are compared with traditional MOSFET-based SRAM cells. As with the conventional cells, the MOSFET-based implementation of the proposed cell power and SNM performance is also very good. The simulation is done with the HSPICE simulation tool using the Stanford University 32[Formula: see text]nm CNTFET model.

scholarly journals A Low-Power Scalable Stream Compute Accelerator for General Matrix Multiply (GEMM)

VLSI Design ◽  
2014 ◽  
Vol 2014 ◽  
pp. 1-11 ◽  
Author(s):  
Antony Savich ◽  
Shawki Areibi
Keyword(s):  
Low Power ◽  
High Performance ◽  
Matrix Multiplication ◽  
Hardware Accelerator ◽  
Power Performance ◽  
Matrix Operations ◽  
Simulated System ◽  
Scalable Hardware ◽  
Functional Prototype ◽  
High Performance Computation

Many applications ranging from machine learning, image processing, and machine vision to optimization utilize matrix multiplication as a fundamental block. Matrix operations play an important role in determining the performance of such applications. This paper proposes a novel efficient, highly scalable hardware accelerator that is of equivalent performance to a 2 GHz quad core PC but can be used in low-power applications targeting embedded systems requiring high performance computation. Power, performance, and resource consumption are demonstrated on a fully-functional prototype. The proposed hardware accelerator is 36× more energy efficient per unit of computation compared to state-of-the-art Xeon processor of equal vintage and is 14× more efficient as a stand-alone platform with equivalent performance. An important comparison between simulated system estimates and real system performance is carried out.

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