FAILURE TOLERANT SYNCHRONOUS AND SELT-TIED CIRCUITS COMPARISON

The article considers the problem of developing synchronous and self-timed (ST) digital circuits that are tolerant to soft errors. Synchronous circuits traditionally use the 2-of-3 voting principle to ensure single failure, resulting in three times the hardware costs. In ST circuits, due to dual-rail signal coding and two-phase control, even duplication provides a soft error tolerance level 2.1 to 3.5 times higher than the triple modular redundant synchronous counterpart. The development of new high-precision software simulating microelectronic failure mechanisms will provide more accurate estimates for the electronic circuits' failure tolerance

A SCALAR BASED ROUTING PROTOCOL APPLIED TO WIRELESS SENSOR NETWORKS

Wireless Sensor Networks motes have a small size, which leads to severe power supply restrictions. Much of the work on conserving power has been undertaken in the domain of routing protocols which deals with sending data in an efficient manner. In this paper a new scalar based protocol is proposed with a combination of multiple sub-base stations, that seeks to enhance the efficiency of protocol in terms of consumption of power and node failure tolerance. All the nodes are divided into regions, with each region having a sub- base station(sBS) and an arbitrary scalar value. Each sBS has lesser power supply and computation power compared to main station, but more of the mentioned metrics with respect to the sensor motes. Previous studies have described various paradigms and metrics for routing protocols and the placement of base stations. In this paper, the said algorithm is proposed, and its efficiency is analysed.