Traffic analysis for on-chip networks design of multimedia applications

Author(s):  
G. Varatkar ◽  
R. Marculescu
Author(s):  
M Meraj Ahmed ◽  
Abhijitt Dhavlle ◽  
Naseef Mansoor ◽  
Purab Sutradhar ◽  
Sai Manoj Pudukotai Dinakarrao ◽  
...  
Keyword(s):  

Author(s):  
Sergi Abadal ◽  
Albert Mestres ◽  
Raul Martinez ◽  
Eduard Alarcon ◽  
Albert Cabellos-Aparicio ◽  
...  
Keyword(s):  

Author(s):  
SOUMYAJIT DEY ◽  
PRAVEEN ROKKAM ◽  
ANUPAM BASU

Embedded multimedia systems often run multiple time-constrained applications simultaneously. To meet the throughput constraints given in the specification, each application must be provided with enough resources by the underlying architecture, which is generally a multiprocessor system-on-chip (MPSoC). For this purpose, a mechanism for task binding and scheduling is required to provide each application with a timing guarantee, keeping in mind the available resources like processor(s) and memory bandwidth. Commonly, synchronous dataflow graphs (SDFGs) are used to model time-constrained multimedia applications. There are resource allocation strategies for SDFGs that help in formulating efficient techniques for calculating the throughput of a bounded and scheduled SDFG. The strategies are effective in terms of run-time and allocated resources. However, there is no unified modeling technique to simultaneously represent the application and the underlying architecture with resource allocation. This paper discusses a novel modeling technique using Colored Timed Petri Nets (CTPNs), which can be used to model the application as well as the architecture and the resource allocation. Such a representation helps in checking properties like liveness and boundedness for the application, taking into account the resource allocation and thus helping in defining satisfactory schedules for the executable tasks.


2016 ◽  
Vol 25 (10) ◽  
pp. 1630005 ◽  
Author(s):  
Marcelo Daniel Berejuck ◽  
Antônio A. Fröhlich

We present the design and evaluation of a high-performance network-on-chip (NoC) focused on telecommunication and multimedia applications that tolerate latency and bandwidth variations. The design is based on a connectionless strategy in which flits from different communication flows are interleaved in the same communication channel. Each flit carries routing information that is used by routers to perform arbitration and scheduling of the corresponding output ports in order to balance channel utilization. In order to compare our approach with others, we introduce an analytic model for the worst-case latency (WCL) of our NoC and recall those of related approaches. Analytic comparisons and experimental data show that our approach keeps average WCL lower for variable-bit-rate multimedia applications than a network based on resource reservation. For these applications, the overall throughput is larger than that of networks that perform resource reservation. A case study based on the proposed NoC shows that the average latency was 28% lower than the WCL expected for the experiment. Indeed, hard real-time flows designed considering the absolute WCL of the network will always meet the requirements of the associated hard real-time tasks, so no deadline can be lost due to network contention.


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