Improving compression ratio, area overhead, and test application time for system-on-a-chip test data compression/decompression

2003 ◽  
Author(s):  
P.T. Gonciari ◽  
B.M. Al-Hashimi ◽  
N. Nicolici
Keyword(s):  
Data Compression ◽  
Test Data ◽  
Compression Ratio ◽  
Test Data Compression ◽  
Application Time ◽  
Test Application Time ◽  
Area Overhead ◽  
Test Application ◽  
System On A Chip

Test data compression of system-on-a-chip (SoC) based on partial runs reversing

2010 ◽  
Vol 24 (1) ◽  
pp. 23-28
Author(s):  
Yiming Ouyang ◽  
Baosheng Zou ◽  
Huaguo Liang ◽  
Xi’e Huang
Keyword(s):  
Data Compression ◽  
Test Data ◽  
Test Data Compression ◽  
System On A Chip

scholarly journals Grouped Scan Slice Repetition Method for Reducing Test Data Volume and Test Application Time

2009 ◽  
Vol E92-D (7) ◽  
pp. 1462-1465 ◽  
Author(s):  
Yongjoon KIM ◽  
Myung-Hoon YANG ◽  
Jaeseok PARK ◽  
Eunsei PARK ◽  
Sungho KANG
Keyword(s):  
Test Data ◽  
Application Time ◽  
Test Application Time ◽  
Test Application ◽  
Data Volume

A Power Efficient Test Data Compression Method on Count Compatible PRL Coding

2015 ◽  
Vol 24 (06) ◽  
pp. 1550084 ◽  
Author(s):  
Haiying Yuan ◽  
Jiaping Mei ◽  
Xun Sun ◽  
K. T. Cheng ◽  
Kun Guo
Keyword(s):  
Power Consumption ◽  
Test Data ◽  
Application Time ◽  
Compression Method ◽  
Scan Testing ◽  
Run Length ◽  
Test Application Time ◽  
Test Application ◽  
Coding Method ◽  
Average Power Consumption

A realistic test sets compression method is proposed to effectively reduce test data volume and test application time during system-on-chip (SoC) scan testing, count compatible pattern run-length (CCPRL) coding method counts the consecutive number of the equal to or contrary to the retained patterns, it modifies the compatible code of variable-length pattern run-length (VPRL) coding rules and adds a count code block to replace original rules for increasing compression ratio. Next, the decoder architecture and the state diagram of finite state machine (FSM) are designed. In addition, the power model of test vectors is analyzed, and the power consumption of scanned-in vectors is roughly evaluated. The six largest ISCAS'89 benchmark circuits verify the proposed coding method has a shorter codeword. Experiment results shows that all compression ratios have been increased as much as possible, test data decompression is lossless, less test application time is consumed, yet the peak power and average power consumption of scanned-in test vector needs to be further improved for modern circuit scan testing.

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