Behavioral phase-noise analysis of charge-pump phase-locked loops

2011 ◽  
Author(s):  
P. Maffezzoni ◽  
S. Levantino ◽  
C. Samori ◽  
A. L. Lacaita ◽  
D. D'Amore ◽  
...  
Keyword(s):  
Phase Noise ◽  
Noise Analysis ◽  
Charge Pump ◽  
Phase Locked Loops ◽  
Behavioral Phase

Folding of Phase Noise Spectra in Charge-Pump Phase-Locked Loops Induced by Frequency Division

2010 ◽  
Vol 57 (9) ◽  
pp. 671-675 ◽  
Author(s):  
Salvatore Levantino ◽  
Luca Collamati ◽  
Carlo Samori ◽  
Andrea L. Lacaita
Keyword(s):  
Phase Noise ◽  
Charge Pump ◽  
Phase Locked Loops ◽  
Frequency Division ◽  
Noise Spectra

scholarly journals A Very Low Reference Spur Phase Offset Technique in Fractional-N Charge pump PLLs

2021 ◽  
Author(s):  
Chembiyan Thambidurai
Keyword(s):  
Phase Noise ◽  
Charge Pump ◽  
Detailed Comparison ◽  
Phase Locked Loops ◽  
Phase Offset ◽  
Reference Spur ◽  
Simulation Results

Fractional-N charge pump phase locked loops (PLLs) suffer from the problem of increased in-band phase noise due to charge pump non-linearity caused by UP/DN chargepump current mismatch. Existing techniques that resolve this problem by introducing phase offset between reference and divide signals cause large reference spurs or increase jitter at PLL output. A very low reference spur phase offset technique is proposed in this work. It produces the lowest reference spurs compared to previously published works. A detailed comparison of the reference spurs caused by the different techniques to introduce phase offset is presented. Simulation results show that the reference spur level generated at the PLL output after applying the proposed technique is 26 dB lower than the existing techniques in the presence of 5% chargepump current mismatch.<br>

scholarly journals PLL DESIGN AND INVESTIGATION IN CMOS

2010 ◽  
Vol 2 (1) ◽  
pp. 54-58
Author(s):  
Jevgenij Charlamov
Keyword(s):  
Phase Noise ◽  
Noise Analysis ◽  
Charge Pump ◽  
Phase Locked Loop ◽  
Voltage Controlled Oscillator ◽  
Functional Blocks ◽  
Oscillator Phase Noise ◽  
A Charge ◽  
The Relationship ◽  
Oscillator Phase

In the article the architecture of a charge pump phase locked loop is shown. The influence on overall system performance of its functional blocks is discussed. Voltage controlled oscillator phase noise analysis is done and the relationship between a charge pump phase locked loop and voltage controlled oscillator phase noises are determined. The requirements and results of the accomplished design are discussed. Area of chip PLL – 150×250 μm2, power consumption – 10 mW and phase noise is –125 dBc/Hz with 1 MHz deviation from central 670 MHz frequency.

scholarly journals A Very Low Reference Spur Phase Offset Technique in Fractional-N Charge pump PLLs

2021 ◽  
Author(s):  
Chembiyan Thambidurai
Keyword(s):  
Phase Noise ◽  
Charge Pump ◽  
Detailed Comparison ◽  
Phase Locked Loops ◽  
Phase Offset ◽  
Reference Spur ◽  
Simulation Results

Fractional-N charge pump phase locked loops (PLLs) suffer from the problem of increased in-band phase noise due to charge pump non-linearity caused by UP/DN chargepump current mismatch. Existing techniques that resolve this problem by introducing phase offset between reference and divide signals cause large reference spurs or increase jitter at PLL output. A very low reference spur phase offset technique is proposed in this work. It produces the lowest reference spurs compared to previously published works. A detailed comparison of the reference spurs caused by the different techniques to introduce phase offset is presented. Simulation results show that the reference spur level generated at the PLL output after applying the proposed technique is 26 dB lower than the existing techniques in the presence of 5% chargepump current mismatch.<br>

Design and noise analysis of a fully-differential charge pump for phase-locked loops

2009 ◽  
Vol 30 (10) ◽  
pp. 105013 ◽  
Author(s):  
Gong Zhichao ◽  
Lu Lei ◽  
Liao Youchun ◽  
Tang Zhangwen
Keyword(s):  
Noise Analysis ◽  
Charge Pump ◽  
Phase Locked Loops ◽  
Fully Differential

Quantization Noise Analysis of Time-to-Digital-Converter-Based All-Digital Phase-Locked Loop and Frequency Discriminators

2016 ◽  
Vol 25 (11) ◽  
pp. 1650131
Author(s):  
Sungkyung Park ◽  
Chester Sungchung Park
Keyword(s):  
Phase Noise ◽  
Noise Analysis ◽  
Low Noise ◽  
Quantization Noise ◽  
Phase Locked Loops ◽  
Digital Converter ◽  
Noise Component ◽  
Time To Digital Converter ◽  
Digital Phase ◽  
Delta Sigma

All-digital phase-locked loops (ADPLLs) based on the time-to-digital converter (TDC) and the frequency discriminator (FD) are modeled and analyzed in terms of quantization effects. Using linear models with quantization noise sources, theoretical analysis and simulation are carried out to obtain the output phase noise of each building block of the TDC-based ADPLL. It is newly derived that the TDC noise component caused by the delta-sigma modulator (DSM) and the finite resolution of the digitally controlled oscillator is not white. Namely, the in-band phase noise caused by the DSM-induced TDC is not white, which is due to the integrate-and-dump and subsampling operations of the TDC. This can give some insight into the design of low-noise ADPLLs. Some structures of delta-sigma FDs, which can serve as an alternative to the TDC, are also newly analyzed in terms of quantization noise, using the derived linear noise model.

A Comprehensive Phase Noise Analysis of Bang-Bang Digital PLLs

2021 ◽  
pp. 1-12
Author(s):  
Luca Avallone ◽  
Mario Mercandelli ◽  
Alessio Santiccioli ◽  
Michael Peter Kennedy ◽  
Salvatore Levantino ◽  
...  
Keyword(s):  
Phase Noise ◽  
Noise Analysis
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