High frequency optical integrated circuit design and first iteration realisation in standard silicon CMOS integrated circuitry

Author(s):  
L.W. Snyman ◽  
A. Bogalecki ◽  
L.M. Canning ◽  
M. Du Plessis ◽  
H. Aharoni
2010 ◽  
Vol 2 (3-4) ◽  
pp. 349-357 ◽  
Author(s):  
Vadim Issakov ◽  
Maciej Wojnowski ◽  
Andreas Thiede ◽  
Robert Weigel

Differential signaling is very common for high frequency integrated circuit design. Accurate multimode de-embedding at multigigahertz frequencies, however, is a major challenge. The differential and common-mode parameters can be obtained by converting the measured four-port nodal S-parameters into the mixed-mode form. Under certain conditions, it is possible to separate the modes and consider only the entries corresponding to the differential S-parameters. This allows to reduce the measured 4 × 4 matrix to a 2 × 2 matrix and consider the differential device as a two-port network. Thus, the standard de-embedding techniques, derived for two-port networks, can be applied to differential S-parameters. The purpose of this paper is to investigate the applicability of this approach for on-wafer measurements. We describe analytically the conditions under which this method is valid. As an example, a 2:1 transformer, manufactured in Infineon's 0.13 μm CMOS (complementary metal-oxide semiconductor) process, has been characterized. On-chip de-embedding structures have been fabricated using the same process. The results obtained using Short-Open, Thru-Line, and Thru-Line-Reflect de-embedding techniques are compared. Additionally, the results are verified by simulation of a device under test having high-mode conversion.


Author(s):  
Hung-Sung Lin ◽  
Ying-Chin Hou ◽  
Juimei Fu ◽  
Mong-Sheng Wu ◽  
Vincent Huang ◽  
...  

Abstract The difficulties in identifying the precise defect location and real leakage path is increasing as the integrated circuit design and process have become more and more complicated in nano scale technology node. Most of the defects causing chip leakage are detectable with only one of the FA (Failure Analysis) tools such as LCD (Liquid Crystal Detection) or PEM (Photon Emission Microscope). However, due to marginality of process-design interaction some defects are often not detectable with only one FA tool [1][2]. This paper present an example of an abnormal power consumption process-design interaction related defect which could only be detected with more advanced FA tools.


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