Comparison of Active and Passive Voltage Contrast for Failure Localization

In many cases of failure localization, passive voltage contrast (PVC) localization method does not work, because it is not possible to charge up conducting structures which supposed to be dark in the SEM and FIB images. The reason for this is leakage currents. In this article, the authors show how they succeeded in overcoming these difficulties by the application of the active voltage contrast (AVC) method as it was described as biased voltage contrast by Campbell and Soden. They identified three main cases where the PVC didn't work but where they succeeded in failure localization with the AVC method. This is illustrated with the use of two case studies. Compared to the optical beam based methods the resolution is much better so a single failing contact of e.g. 70 nm technology can clearly be identified which cannot be done by TIVA or OBIRCH.

Combine Micro-Probing and OBIRCH to Catch Non-Recognizable Fault in RF and Mixed-Mode Integrated Circuits

Highly-integrated radio frequency and mixed-mode devices that are manufactured in deep-submicron or more advanced CMOS processes are becoming more complex to analyze. The increased complexity presents us with many eccentric failure mechanisms that are uniquely different from traditional failure mechanisms found during failure analysis on digital logic applications. This paper presents a novel methodology to overcome the difficulties and discusses two case studies which demonstrate the application of the methodology. Through the case studies, the methodology was proven to be a successful approach. It is also proved how this methodology would work for such non-recognizable failures.

Using Statistical Methods to Optimize Patterning Parameters for Tungsten Deposition

Circuit edit and failure analysis require tungsten deposition parameters to accomplish different goals. Circuit edit applications desire low resistivity values for rewiring, while failure analysis requires high deposition rates for capping layers. Tungsten deposition can be a well controlled process for a variety of beam parameters. For circuit edit, tungsten resistivity approaching below 150 µohm-cm and 50 μm3/nC is predicted. Material deposition rates of 80 μm3/nC can be achieved with reasonable pattern accuracy using defocus as a parameter.

Concepts for In Situ Diagnostics in Analog Microelectronic Circuits

Comprehensive in situ (designed-in) diagnostic capabilities have been incorporated into digital microelectronic systems for years, yet similar capabilities are not commonly incorporated into the design of analog microelectronics. And as feature sizes shrink and back end interconnect metallization becomes more complex, the need for effective diagnostics for analog circuits becomes ever more critical. This paper presents concepts for incorporating in situ diagnostic capability into analog circuit designs. Aspects of analog diagnostic system architecture are discussed as well as nodal measurement scenarios for common signal types. As microelectronic feature sizes continue to shrink, diagnostic capabilities such as those presented here will become essential to the process of fault localization in analog circuits.

PCB Related Field Failures with ImAg Surface Finishes

PCB surface finishes like Immersion silver (ImAg) are commonly used in Pb-free manufacturing environments following RoHS legislation. With this transition, however the numbers of field failures associated with electrochemical migration, copper sulphide corrosion, via barrel galvanic corrosion are on a steady rise. More often than not ImAg surfaces seem to assist these failing signatures. As computers penetrate into emerging markets with humid and industrialized environments there is a greater concern on the reliability and functionality of these electronic components.

Case Study and Fault Modeling for Wrong Redundancy Evaluation on DRAM Devices

The characterization of failure modes of DRAM is often straight forward if array related hard failures with specific addresses for localization are concerned. The paper presents a case study of a bitline oriented failure mode connected to a redundancy evaluation in the DRAM periphery. The failure mode analysis and fault modeling focus both on the root-cause and on the test aspects of the problem.

Localized Die Metallization Damage Induced During Laser-Marking of a Semiconductor Package

This paper presents a new fail mechanism for laser-marking induced die damage. Discovered during package qualification, silica spheres – commonly used as fillers in the molding material, was shown to act as a propagation medium that promote the direct interaction of the scribing laser beam and the die surface. Critical to the understanding of the fail mechanism is the deprocessing technique devised to allow layer by layer examination of the metallization and passivation layers in an encapsulated silicon die. The technique also made possible the inspection of the molding compound profile directly on top of the affected die area.

Reduction of Acquisition Time for RIL, SDL, and LADA

Although RIL, SDL and LADA are slightly different, the main operating principle is the same and the theory for defect localization presented in this paper is applicable to all three methods. Throughout this paper the authors refer to LADA, as all experimental results in this paper were obtained with a 1064nm laser on defect free circuits. This paper first defines mathematically what 'signal strength' actually means in LADA and then demonstrates a statistical model of the LADA situation that explains the optimal conditions for signal collection and the parameters involved. The model is tested against experimental data and is also used to optimise the acquisition time. Through this model, equations were derived for the acquisition time needed to discern a LADA response from the background noise. The model offers a quantitative tool to estimate the feasibility of a given LADA measurement and a guide to optimising the required experimental set-up.

A Case Study of Defects Due to Process-Design Interaction in Nano Scale Technology

The difficulties in identifying the precise defect location and real leakage path is increasing as the integrated circuit design and process have become more and more complicated in nano scale technology node. Most of the defects causing chip leakage are detectable with only one of the FA (Failure Analysis) tools such as LCD (Liquid Crystal Detection) or PEM (Photon Emission Microscope). However, due to marginality of process-design interaction some defects are often not detectable with only one FA tool [1][2]. This paper present an example of an abnormal power consumption process-design interaction related defect which could only be detected with more advanced FA tools.

Ion Beam Imaging Methodology of Invisible Metal under Insulator Using High Energy Electron Beam Charging

Focused ion beam (FIB) is a popular tool for physical failure analysis (FA), especially for circuit repair. FIB is especially useful on advanced technology where the FIB is used to modify the circuit for new layout verification or electrical measurement. The samples are prepared till inter-metal dielectric (IMD), then a hole is dug or a metal is deposited or oxide is deposited by FIB. A common assumption is made that metal under oxide can not be seen by FIB. But a metal ion image is desired for further action. Dual beam, FIB and Scanning Electron Microscope (SEM), tools have a special advantage. When switching back and forth from SEM to FIB the observation has been made that the metal lines can be imaged. The details of this technique will be discussed below.