Numerical Simulation and Thermal Failure Analysis of SOM Package

Author(s):  
Jae Choon Kim ◽  
Jin Taek Chung ◽  
Won Suk Lee ◽  
Gyoung Bum Kim ◽  
Dong Jin Lee ◽  
...  
Author(s):  
Vikash Kumar ◽  
Devraj Karthikeyan

Abstract Fault localization is a common failure analysis process that is used to detect the anomaly on a faulty device. The Infrared Lock-In Thermography (LIT) is one of the localization techniques which can be used on the packaged chips for identifying the heat source which is a result of active damage. This paper extends the idea that the LIT analysis for fault localization is not only limited to the devices within the silicon die but it also highlights thermal failure indications of other components on the PCB (like capacitors, FETs etc on a system level DC-DC μmodule). The case studies presented demonstrate the effectiveness of using LIT in the Failure analysis process of a system level DC-DC μmodule regulator


2014 ◽  
Vol 974 ◽  
pp. 293-297
Author(s):  
Xiao Ping Wang ◽  
Xiong Xia ◽  
Kun Hu ◽  
Jin Cai Feng

The progressive failure study of the slope is a challenging problem. There exist a lot of problems at present in this area, it’s necessary to do some summaries. This paper did some analysis and discussion from four aspects: limit equilibrium analysis of the slope progressive failure; test analysis of the slope progressive failure, numerical simulation of the slope progressive failure and limit equilibrium analysis on the basis of finite element, and provided some reference for slope progressive failure study.


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