scholarly journals Design of a Second Order CMOS Sigma-Delta A/D Converter with a 150 MHz Clock Rate

Author(s):  
B. Hallgren
Keyword(s):  
2001 ◽  
Vol 11 (1) ◽  
pp. 554-557 ◽  
Author(s):  
T. Hashimoto ◽  
H. Hasegawa ◽  
S. Nagasawa ◽  
H. Suzuki ◽  
K. Miyahara ◽  
...  

2004 ◽  
Vol 1 (3) ◽  
pp. 37-44 ◽  
Author(s):  
Dragisa Milovanovic ◽  
Milan Savic ◽  
Miljan Nikolic

As a part of wider project sigma-delta modulator was designed. It represents an A/D part of a power meter IC. Requirements imposed were: SNDR and dynamic range > 50 dB for maximum input swing of 250 mV differential at 50 Hz. Over sampling ratio is 128 with clock frequency of 524288 Hz which gives bandwidth of 2048 Hz. Circuit is designed in 3.3 V supply standard CMOS 0.35 ?m technology.


2014 ◽  
Vol 18 (2) ◽  
pp. 263-271
Author(s):  
Chulkyu Park ◽  
Kichang Jang ◽  
Hyojae Kim ◽  
Joongho Choi

Author(s):  
Rochelle Marie F. Amistoso ◽  
Michael Joe A. Bautista ◽  
Rafael Karlo D.P. Delos Santos ◽  
Joana Rochelle R. Ortiz ◽  
Louis P. Alarcon ◽  
...  

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