scholarly journals Second-order sigma-delta modulator in standard cmos technology

2004 ◽  
Vol 1 (3) ◽  
pp. 37-44 ◽  
Author(s):  
Dragisa Milovanovic ◽  
Milan Savic ◽  
Miljan Nikolic
Keyword(s):  
Dynamic Range ◽  
Cmos Technology ◽  
Second Order ◽  
Clock Frequency ◽  
Sigma Delta Modulator ◽  
Sigma Delta ◽  
Power Meter ◽  
Sampling Ratio

As a part of wider project sigma-delta modulator was designed. It represents an A/D part of a power meter IC. Requirements imposed were: SNDR and dynamic range > 50 dB for maximum input swing of 250 mV differential at 50 Hz. Over sampling ratio is 128 with clock frequency of 524288 Hz which gives bandwidth of 2048 Hz. Circuit is designed in 3.3 V supply standard CMOS 0.35 ?m technology.

The Design of CIFF Structure Three-Order Switched-Capacitor Sigma-Delta Modulator

2012 ◽  
Vol 433-440 ◽  
pp. 5727-5732
Author(s):  
Jun Han ◽  
Wei Dong Wang
Keyword(s):  
Dynamic Range ◽  
Supply Voltage ◽  
Optimization Technique ◽  
Cmos Technology ◽  
Switched Capacitor ◽  
Clock Frequency ◽  
Sigma Delta Modulator ◽  
Sigma Delta ◽  
Transconductance Amplifier ◽  
A Chain

This paper presents the design and implementation of a single-loop three-order switched-capacitor sigma-delta modulator(SDM) with a standard 0.18um CMOS technology. A current optimization technique is utilized in proposed design to reduce the power of operational transconductance amplifier(OTA).Using a chain of Integrators with weighted feed-forward summation(CIFF) structure and optimized single-stage class-A OTA with positive feed-back to minimize the power consumption. The SDM has been presented with an over-sampling ratio of 128,clock frequency 6.144MHz,24kHz band- width, and achieves a peak SNR of 100dB,103dB dynamic range. The whole circuits consume 2.87mW from a single 1.8V supply voltage.

AN ENERGY EFFICIENT SECOND-ORDER ΣΔ MODULATOR BASED ON THE POWER AND DELAY OPTIMIZATION OF CBSC IIR FILTER

2012 ◽  
Vol 21 (08) ◽  
pp. 1240024
Author(s):  
MEHDI TAGHIZADEH ◽  
AMMAR RAHIMI KAZEROONI ◽  
MAJID ZAMANI ◽  
PAYMAN GOODARZI
Keyword(s):  
Dynamic Range ◽  
Second Order ◽  
Sigma Delta Modulator ◽  
Sigma Delta ◽  
Iir Filter ◽  
Op Amps ◽  
Sampling Ratio ◽  
And Performance ◽  
Σδ Modulator ◽  
Gain Stage

In this paper a second-order low distortion Sigma-Delta Modulator (ΣΔM) with utilization of Comparator-Based Switched-Capacitor (CBSC)-based IIR filter, is explored. The advantages of this new structure are justified by the reduction of power and area. For this purpose IIR filter block can be made with single CBSC gain stage that has the same accuracy and performance of second-order filter with two Op-amps. The design of CBSC gain stages is intended to minimize the power consumption, and maximize Modulator performance. As shown in the simulation result, for a 20-KHz signal bandwidth, the modulator achieves a dynamic range of 70.2 dB and a peak signal-to-noise and distortion ratio (SNDR) of 68 dB with an over-sampling ratio of 64. In addition it consumes only 198 μW from a 1.8-V power supply at 2.56 MS/s.

scholarly journals Current mode sigma-delta modulator designed with the help of transistor’s size optimization tool

2015 ◽  
Vol 63 (4) ◽  
pp. 919-922 ◽  
Author(s):  
P. Śniatała ◽  
M. Naumowicz ◽  
A. Handkiewicz ◽  
S. Szczęsny ◽  
J.L.A. de Melo ◽  
...  
Keyword(s):  
Current Mode ◽  
Cmos Technology ◽  
Clock Frequency ◽  
Mode Structure ◽  
Sigma Delta Modulator ◽  
Sigma Delta ◽  
Current Output ◽  
Image Pixels ◽  
Time Loop ◽  
A Current

Abstract The paper presents a second order current mode sigma-delta modulator designed with the help of a new elaborated tool to optimize the transistor sizes. The circuit is composed of two continuous time loop filters, a current comparator and a one bit DAC with a current output. The resulting circuit, designed in a 65 nm 1.2 V CMOS technology, has a bandwidth of 2 MHz for a clock frequency of 250 MHz. The electrical simulation results show that it achieves a maximum signal-to-noise-plus-distortion ratio (SNDR) of 53.6 dB while dissipating 93 μW, which corresponds to an efficiency of 59.7 fJ/conv. The fully current mode structure makes the circuit suitable to be applied in a current mode signal processing like biosensors or image pixels arrays.

A RE-CONFIGURABLE ARCHITECTURE FOR SWITCHED CAPACITOR SIGMA-DELTA ANALOG-TO-DIGITAL CONVERSION

2013 ◽  
Vol 22 (09) ◽  
pp. 1340012
Author(s):  
KAREN WAN ◽  
GIGI CHAN ◽  
WILLIAM WONG ◽  
KAM CHUEN WAN ◽  
BRYCE YAU ◽  
...  
Keyword(s):  
Fourth Order ◽  
Cmos Technology ◽  
Second Order ◽  
Switched Capacitor ◽  
Noise Shaping ◽  
Digital Conversion ◽  
Sigma Delta Modulator ◽  
Sigma Delta ◽  
Analog To Digital ◽  
Analog To Digital Conversion

A re-configurable switched capacitor sigma-delta analog-to-digital conversion architecture1,2 is proposed. The architecture consists of a MASH sigma delta modulator with nth lower-order (first- or second-order) loops cascaded together. Each loop can be powered on or off operating in high or low performance mode, according to application needs. The architecture can be configured to optimize performance and power consumption for specific resolution and applications. The architecture is proven by means of a prototype, implemented as a fourth-order and fabricated in a standard 0.18 um CMOS technology. The outputs of both high performance mode (fourth-order) and medium performance mode (second-order, first loop ON) are measured to demonstrate the configurability. The FFT demonstrates that the noise shaping for the fourth-order modulator is better than that of the second-order modulator with steeper noise shaping slope.

A High-Performance Sigma-Delta Modulator in 0.18μm CMOS Technology

2014 ◽  
Vol 519-520 ◽  
pp. 1085-1088
Author(s):  
Ying Qi Qian ◽  
Chang Chun Zhang ◽  
Zhong Chao Liu ◽  
Lei Lei Liu ◽  
Yu Rong Luan ◽  
...  
Keyword(s):  
Radio Frequency Identification ◽  
High Speed ◽  
High Performance ◽  
Dynamic Range ◽  
Low Voltage ◽  
Intermediate Frequency ◽  
Cmos Technology ◽  
High Gain ◽  
Sigma Delta Modulator ◽  
Sigma Delta

Sigma-Delta (∑∆) modulators are commonly used in high-resolution analog-to-digital converters (ADCs). In this paper, a high-performance modulator targeted for ultra-high-frequency (UHF) radio-frequency identification (RFID) zero-intermediate frequency (ZIF) receivers is designed in standard 0.18μm CMOS technology. The modulator has been designed with switched-capacitor (SC) integrators employing gain-boosted operational amplifiers, voltage comparators and nonoverlapping clock generators to satisfy such requirements as high gain, low voltage and wide bandwidth. The behavioral-level modeling and circuit-level design are carried out with MATLAB/Simulink and Cadence/SpectreRF, respectively. Ultimately, the high-speed and low-power realization of a second-order single-bit modulator with an oversampling ratio (OSR) of 32 is presented. Simulation results shown that, from a 1.8V supply, operated at a sampling frequency of 64MHz, a dynamic range of 53.4dB over a signal bandwidth of 1MHz is achieved.

Design of a Second-Order Sigma-Delta Modulator

2014 ◽  
Vol 644-650 ◽  
pp. 3797-3801
Author(s):  
Min Guo ◽  
Hong Hui Deng ◽  
Bo Wen Ding ◽  
Yong Sheng Yin
Keyword(s):  
Power Supply ◽  
Circuit Simulation ◽  
Cmos Technology ◽  
Second Order ◽  
System Level ◽  
Sigma Delta Modulator ◽  
Sigma Delta ◽  
Noise Rate ◽  
Folded Cascode ◽  
Simulation Results

A second-order single bit Sigma - Delta modulator which can be applied to pressure sensor is designed in this paper.The modulator uses switched-capacitor circuit,and the operational amplifier adopts a differential folded-cascode structure with PMOS tube as input. Optimizes the coefficients at the system level design using Simulink tool. The schematic simulation and analysis is by the tools of Spectre and MATLAB with Global Foundry 0.35um CMOS technology. The modulator with oversampling rate of 256 is designed at the 3.3V power supply. Finally, this paper shows the circuit simulation results of the sigma-delta modulator whose signal-noise rate is 103.9dB and resolution is 16.97bits.

scholarly journals Second-order Sigma-Delta Modulator for Mobile BMIC Applications

2014 ◽  
Vol 18 (2) ◽  
pp. 263-271
Author(s):  
Chulkyu Park ◽  
Kichang Jang ◽  
Hyojae Kim ◽  
Joongho Choi
Keyword(s):  
Second Order ◽  
Sigma Delta Modulator ◽  
Sigma Delta
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