Design margin elimination in a near-threshold timing error masking-aware 32-bit ARM Cortex M0 in 40nm CMOS

ESSCIRC 2017 - 43rd IEEE European Solid State Circuits Conference ◽

10.1109/esscirc.2017.8094549 ◽

2017 ◽

Author(s):

Hans Reyserhove ◽

Wim Dehaene

Keyword(s):

Timing Error ◽

Error Masking ◽

Design Margin ◽

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Energy and Delay Tradeoffs of Soft-Error Masking for 16-nm FinFET Logic Paths: Survey and Impact of Process Variation in the Near-Threshold Region

IEEE Transactions on Circuits & Systems II Express Briefs ◽

10.1109/tcsii.2016.2587763 ◽

2017 ◽

Vol 64 (6) ◽

pp. 695-699 ◽

Author(s):

Faris S. Alghareb ◽

Rizwan A. Ashraf ◽

Ahmad Alzahrani ◽

Ronald F. DeMara

Keyword(s):

Process Variation ◽

Threshold Region ◽

Error Masking ◽

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GreenTPU: Predictive Design Paradigm for Improving Timing Error Resilience of a Near-Threshold Tensor Processing Unit

IEEE Transactions on Very Large Scale Integration (VLSI) Systems ◽

10.1109/tvlsi.2020.2985057 ◽

2020 ◽

Vol 28 (7) ◽

pp. 1557-1566

Author(s):

Pramesh Pandey ◽

Prabal Basu ◽

Koushik Chakraborty ◽

Sanghamitra Roy

Keyword(s):

Error Resilience ◽

Processing Unit ◽

Timing Error ◽

Design Paradigm ◽

Predictive Design ◽

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Time Borrowing Flip-Flop architecture for error masking in near threshold voltage regime

Journal of Physics Conference Series ◽

10.1088/1742-6596/1917/1/012001 ◽

2021 ◽

Vol 1917 (1) ◽

pp. 012001

Author(s):

Abhinav Raj ◽

Diwakar Arora ◽

Aman Chaurasia ◽

S. Indu

Keyword(s):

Threshold Voltage ◽

Flip Flop ◽

Time Borrowing ◽

Error Masking ◽

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A near threshold error resilient processor based on dynamic timing error prediction and within-a-cycle timing error correction

2015 IEEE 11th International Conference on ASIC (ASICON) ◽

10.1109/asicon.2015.7517178 ◽

2015 ◽

Author(s):

Taotao Zhu ◽

Xiaoyan Xiang ◽

Chen Chen ◽

Jianyi Meng

Keyword(s):

Error Correction ◽

Error Prediction ◽

Timing Error ◽

Error Resilient ◽

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A True Single-Phase Error Masking Flip-Flop with Reduced Clock Power for Near-Threshold Designs

Communications in Computer and Information Science - VLSI Design and Test ◽

10.1007/978-981-32-9767-8_32 ◽

2019 ◽

pp. 371-382 ◽

Author(s):

Priyamvada Sharma ◽

Bishnu Prasad Das

Keyword(s):

Single Phase ◽

Phase Error ◽

Flip Flop ◽

Error Masking ◽

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Margin Elimination Through Timing Error Detection in a Near-Threshold Enabled 32-bit Microcontroller in 40-nm CMOS

IEEE Journal of Solid-State Circuits ◽

10.1109/jssc.2018.2821121 ◽

2018 ◽

Vol 53 (7) ◽

pp. 2101-2113 ◽

Author(s):

Hans Reyserhove ◽

Wim Dehaene

Keyword(s):

Error Detection ◽

Timing Error ◽

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Design Margin Reduction Through Completion Detection in a 28-nm Near-Threshold DSP Processor

IEEE Journal of Solid-State Circuits ◽

10.1109/jssc.2021.3106245 ◽

2021 ◽

pp. 1-1

Author(s):

Roel Uytterhoeven ◽

Wim Dehaene

Keyword(s):

Design Margin ◽

28 Nm ◽

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A Metastability Immune Timing Error Masking Flip-Flop for Dynamic Variation Tolerance

Proceedings of the 26th edition on Great Lakes Symposium on VLSI - GLSVLSI '16 ◽

10.1145/2902961.2902976 ◽

2016 ◽

Author(s):

Govinda Sannena ◽

Bishnu Prasad Das

Keyword(s):

Timing Error ◽

Flip Flop ◽

Dynamic Variation ◽

Variation Tolerance ◽

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Timing error masking by exploiting operand value locality in SIMD architecture

2014 IEEE 32nd International Conference on Computer Design (ICCD) ◽

10.1109/iccd.2014.6974667 ◽

2014 ◽

Author(s):

Jaehyeong Sim ◽

Jun-Seok Park ◽

Seungwook Paek ◽

Lee-Sup Kim

Keyword(s):

Timing Error ◽

Simd Architecture ◽

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Metastability immune and area efficient error masking flip-flop for timing error resilient designs

Integration ◽

10.1016/j.vlsi.2017.11.006 ◽

2018 ◽

Vol 61 ◽

pp. 101-113 ◽

Author(s):

Govinda Sannena ◽

Bishnu Prasad Das

Keyword(s):

Timing Error ◽

Flip Flop ◽

Error Resilient ◽

Error Masking ◽

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