A scaleable FIR filter using 32-bit floating-point complex arithmetic on a configurable computing machine

2002 ◽  
Author(s):  
A. Walters ◽  
P. Athanas
Keyword(s):  
Fir Filter ◽  
Floating Point ◽  
Configurable Computing ◽  
Complex Arithmetic ◽  
Computing Machine

scholarly journals FIR Filter Design using Floating Point Column Bypassing Technique

2019 ◽  
Vol 8 (2S4) ◽  
pp. 409-413 ◽  
Keyword(s):  
Signal Processing ◽  
Power Consumption ◽  
Truncation Error ◽  
Filter Design ◽  
Fir Filter ◽  
Floating Point ◽  
Switching Activity ◽  
Software And Hardware ◽  
Fir Filter Design ◽  
Dsp Applications

This paper presents the design of floating point fixed-width multiplier using column bypassing technique for signal processing applications. The designed fixed-width multiplier provides less power consumption due to the reduction of switching activity in the operands of the partial products. This is the key element of the Multiply-accumulate (MAC) unit for enhancing its performance. The proposed MAC can be implemented in a FIR filter for DSP applications. To improve the accuracy of the FIR filter, various rounding methods have been used to solve the truncation error in the product. The power consumption is 10% lesser than conventional fixed-width multiplier and the accuracy also have been improved. The output response of the proposed filter will be simulated in the virtual software and hardware environment with the MATLAB software.

scholarly journals FPGA Implementation of Efficient FIR Filter

2020 ◽  
Vol 9 (3) ◽  
pp. 3410-3412
Keyword(s):  
Programming Language ◽  
Filter Design ◽  
Fir Filter ◽  
Fpga Implementation ◽  
Floating Point ◽  
Matlab Software ◽  
Dynamic Power ◽  
Main Target ◽  
Filter Operation ◽  
Fir Filter Design

Improve the functionality of an FIR Filter by modifying the internal components used to design a filter. These past years have seen some great improvements in the speed, power, and area of the filter. Here, we will, therefore, use an ALU-based algorithm to design our FIR filter. The internal components of the ALU block will be an Adder and a Multiplier. A Floating point Adder and a Floating Point Multiplier will be the basic backbone of the ALU block, which finally will be used to design and implement our FIR filter design. Therefore, the parameters of the area are our main target but we will also see the power consumed by the Filter operation, both static and dynamic power consumed will be seen. The programming language will be written in VERILOG and the simulation and implementation of the design will be done by the help of Xilinx ISE suite version. One important aspect is that there will be 16 input samples and 16 coefficients which will be directly from a 16 tap filter. These coefficients and input values will be generated through MATLAB software.

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