Low power components for 1 Gb/s optical communications: A single-chip 10-channel optical receiver and a clock recovery circuit

2002 ◽  
Author(s):  
R.M. Hickling ◽  
R.A. Kot ◽  
M.N. Yagi ◽  
R. Nagarajan ◽  
W.J. Sha ◽  
...  
Keyword(s):  
Low Power ◽  
Optical Communications ◽  
Optical Receiver ◽  
Clock Recovery ◽  
Single Chip

Low-Power and Reference-Less Data and Clock Recovery Circuit for Visible Light Receivers

2018 ◽  
Author(s):  
Ming-Cheng Liu ◽  
Paul C.-P. Chao ◽  
Soh Sze Khiong
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Visible Light ◽  
Low Voltage ◽  
Supply Voltage ◽  
Clock And Data Recovery ◽  
Optical Receiver ◽  
Clock Recovery ◽  
Cmos Process ◽  
Rf Receiver

In this paper a low power all-digital clock and data recovery (ADCDR) with 1Mhz frequency has been proposed. The proposed circuit is designed for optical receiver circuit on the battery-less photovoltaic IoT (Internet of Things) tags. The conventional RF receiver has been replaced by the visible light optical receiver for battery-less IoT tags. With this proposed ADCDR a low voltage, low power consumption & tiny IoT tags can be fabricated. The proposed circuit achieve the maximum bandwidth of 1MHz, which is compatible with the commercial available LED and light sensor. The proposed circuit has been fabricated in TSMC 0.18um 1P6M standard CMOS process. Experimental results show that the power consumption of the optical receiver is approximately 5.58uW with a supply voltage of 1V and the data rate achieves 1Mbit/s. The lock time of the ADCDR is 0.893ms with 3.31ns RMS jitter period.

scholarly journals Low Power Consumption Digital Clock Recovery Circuit Based on Threshold Crossing

2016 ◽  
Vol 67 (6) ◽  
pp. 433-438
Author(s):  
Dragana Perić ◽  
Miroslav Perić
Keyword(s):  
Mathematical Model ◽  
Power Consumption ◽  
Low Power ◽  
Phase Error ◽  
Low Complexity ◽  
Clock Recovery ◽  
Low Power Consumption ◽  
Single Chip ◽  
Digital Clock ◽  
Measurement Methodology

Abstract In this paper a new structure of digital clock recovery — DCR circuit is presented. The main features of this DCR are: low complexity design, low power consumption and a single system clock operation. Thus, multiple instantiation of this type of DCR on a single chip is not complex. Due to this, such DCR can target application in energy-efficient cognitive radio systems with carrier aggregation. For performance evaluation, we have derived Markov chain based mathematical model for peak-to-peak and root mean square jitter performance analysis. The stability problem of this model, rising from the fact that some phase error states have several orders of magnitude lower probabilities than the others, is solved using mathematical apparatus for symbolic analysis. The mathematical model validity is examined by laboratorial measurements of proposed DCR for 4-PAM signal. The measurement methodology and results are described in details.

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