Implementation of digital logic circuit in artificial neural network with floating point arithmetic using verilog HDL

2017 ◽  
Author(s):  
Aisha Jangid ◽  
Shraddha Kabra
Keyword(s):  
Neural Network ◽  
Artificial Neural Network ◽  
Logic Circuit ◽  
Digital Logic ◽  
Floating Point ◽  
Verilog Hdl ◽  
Floating Point Arithmetic ◽  
Artificial Neural ◽  
Point Arithmetic

Implementation of Low Power Pipelined 64-bit RISC Processor with Unbiased FPU on CPLD

2016 ◽  
Vol 5 (2) ◽  
pp. 118
Author(s):  
J. Vijay Kumar ◽  
B. Naga Raju ◽  
M. Vasu Babu ◽  
T. Ramanjappa
Keyword(s):  
Low Power ◽  
Arithmetic Operation ◽  
Floating Point ◽  
Double Precision ◽  
Verilog Hdl ◽  
Logical Function ◽  
Floating Point Arithmetic ◽  
Risc Processor ◽  
Operation Results ◽  
Point Arithmetic

This article represents the implementation of low power pipelined 64-bit RISC processor on Altera MAXV CPLD device.  The design is verified for arithmetic operations of both fixed and floating point numbers, branch and logical function of RISC processor. For all the jump instruction, the processor architecture will automatically flush the data in the pipeline, so as to avoid any misbehavior. This processor contains FPU unit, which supports double precision IEEE-754 format operations very accurately. The simulation results have been verified by using ModelSim software. The ALU operations and double precision floating point arithmetic operation results are displayed on 7-Segments. The necessary code is written in Verilog HDL.

scholarly journals FPGA-based architecture of hybrid multilayered perceptron neural network

2019 ◽  
Vol 14 (2) ◽  
pp. 949 ◽  
Author(s):  
Lee Yee Ann ◽  
P. Ehkan ◽  
M. Y. Mashor ◽  
S. M. Sharun
Keyword(s):  
Neural Network ◽  
Activation Function ◽  
Floating Point ◽  
Output Node ◽  
Floating Point Arithmetic ◽  
Output Layer ◽  
Current Activation ◽  
Multilayered Perceptron ◽  
Point Arithmetic

<span lang="EN-MY">The HMLP is an ANN similar to the MLP, but with extra weighted connections that connect the input nodes directly to the output nodes. The architecture of the HMLP neural network for implementation on FPGA is proposed. The HMLP architecture is designed to be concurrent to demonstrate the parallel nature of the HMLP where each hidden or output node within the same hidden or output layer of the HMLP can calculate its output independently. The HMLP architecture is designed to be modular as well, such that if modification to a module is necessary, only the specific module need to be modified and all other modules can be retained. This modularity will be especially helpful when different activation function is to be swapped in to replace current activation function. All calculations in the HMLP are performed in floating-point arithmetic. The HMLP architecture is compiled, simulated and finally implemented on the Cyclone V FPGA of DE1-SoC board. The simulation outcome and FPGA outputs showed that the developed HMLP architecture is able to calculate correct output values for all test datasets.</span>

Autofluorescence spectroscopy of oral leukoplakia using an artificial neural network

2000 ◽  
Vol 25 (4) ◽  
pp. 325-325
Author(s):  
J.L.N. Roodenburg ◽  
H.J. Van Staveren ◽  
N.L.P. Van Veen ◽  
O.C. Speelman ◽  
J.M. Nauta ◽  
...  
Keyword(s):  
Neural Network ◽  
Artificial Neural Network ◽  
Oral Leukoplakia ◽  
Autofluorescence Spectroscopy ◽  
Artificial Neural

1902: Is Steinstrasse After ESWL of Renal Stones Predictable? Artificial Neural Network Analysis

2004 ◽  
Vol 171 (4S) ◽  
pp. 502-503
Author(s):  
Mohamed A. Gomha ◽  
Khaled Z. Sheir ◽  
Saeed Showky ◽  
Khaled Madbouly ◽  
Emad Elsobky ◽  
...  
Keyword(s):  
Neural Network ◽  
Artificial Neural Network ◽  
Network Analysis ◽  
Renal Stones ◽  
Neural Network Analysis ◽  
Artificial Neural Network Analysis ◽  
Artificial Neural
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