The measurement method of 2D distribution of EMI in the on-chip power distribution network

2016 International Conference on Integrated Circuits and Microsystems (ICICM) ◽

10.1109/icam.2016.7813605 ◽

2016 ◽

Author(s):

Yibin Wang ◽

Lin Yan ◽

Tao Su ◽

Zixin Wang

Keyword(s):

Power Distribution ◽

Measurement Method ◽

Distribution Network ◽

Power Distribution Network ◽

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A Novel Design Methodology of the On-Chip Power Distribution Network Enhancing the Performance and Suppressing EMI of the SoC

2007 IEEE International Symposium on Circuits and Systems ◽

10.1109/iscas.2007.378049 ◽

2007 ◽

Author(s):

Hirokazu Tohya ◽

Noritaka Toya

Keyword(s):

Power Distribution ◽

Design Methodology ◽

Distribution Network ◽

Power Distribution Network ◽

On Chip ◽

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Unconditionally stable explicit method for the fast 3-D simulation of on-chip power distribution network

2013 IEEE 63rd Electronic Components and Technology Conference ◽

10.1109/ectc.2013.6575710 ◽

2013 ◽

Author(s):

Tadatoshi Sekine ◽

Hideki Asai

Keyword(s):

Power Distribution ◽

Distribution Network ◽

Explicit Method ◽

Power Distribution Network ◽

Unconditionally Stable ◽

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Worst-Case Noise Area Prediction of On-Chip Power Distribution Network

Proceedings of SLIP (System Level Interconnect Prediction) on System Level Interconnect Prediction Workshop - SLIP '14 ◽

10.1145/2633948.2633950 ◽

2014 ◽

Author(s):

Xiang Zhang ◽

Jingwei Lu ◽

Yang Liu ◽

Chung-Kuan Cheng

Keyword(s):

Power Distribution ◽

Distribution Network ◽

Power Distribution Network ◽

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Unconditionally stable explicit method for the fast 3-D simulation of on-chip power distribution network with through silicon via

2013 18th Asia and South Pacific Design Automation Conference (ASP-DAC) ◽

10.1109/aspdac.2013.6509550 ◽

2013 ◽

Author(s):

T. Sekine ◽

H. Asai

Keyword(s):

Power Distribution ◽

Distribution Network ◽

Explicit Method ◽

Power Distribution Network ◽

Unconditionally Stable ◽

Through Silicon Via ◽

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System power distribution network theory and performance with various noise current stimuli including impacts on chip level timing

2009 IEEE Custom Integrated Circuits Conference ◽

10.1109/cicc.2009.5280742 ◽

2009 ◽

Author(s):

Larry Smith ◽

Shishuang Sun ◽

Peter Boyle ◽

Bozidar Krsnik

Keyword(s):

Network Theory ◽

Power Distribution ◽

Distribution Network ◽

Power Distribution Network ◽

Noise Current ◽

And Performance ◽

On Chip ◽

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Design of on-chip linear voltage regulator module and measurement of power distribution network noise fluctuation at high-speed output buffer

2016 IEEE Electrical Design of Advanced Packaging and Systems (EDAPS) ◽

10.1109/edaps.2016.7874396 ◽

2016 ◽

Author(s):

Manho Lee ◽

Heegon Kim ◽

Sukjin Kim ◽

Joungho Kim ◽

Jonghyun Cho ◽

...

Keyword(s):

Power Distribution ◽

Distribution Network ◽

Voltage Regulator ◽

Output Buffer ◽

Power Distribution Network ◽

On Chip ◽

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Simultaneous switching noise and resonance analysis of on-chip power distribution network

Proceedings International Symposium on Quality Electronic Design ◽

10.1109/isqed.2002.996723 ◽

2003 ◽

Author(s):

Geng Bai ◽

I.N. Hajj

Keyword(s):

Power Distribution ◽

Distribution Network ◽

Switching Noise ◽

Power Distribution Network ◽

Resonance Analysis ◽

Simultaneous Switching Noise ◽

On Chip ◽

Simultaneous Switching

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Parallel partitioning based on-chip power distribution network analysis using locality acceleration

2009 10th International Symposium on Quality of Electronic Design ◽

10.1109/isqed.2009.4810391 ◽

2009 ◽

Author(s):

Zhiyu Zeng ◽

Peng Li ◽

Zhuo Feng

Keyword(s):

Network Analysis ◽

Power Distribution ◽

Distribution Network ◽

Power Distribution Network ◽

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Parallel On-Chip Power Distribution Network Analysis on Multi-Core-Multi-GPU Platforms

IEEE Transactions on Very Large Scale Integration (VLSI) Systems ◽

10.1109/tvlsi.2010.2059718 ◽

2011 ◽

Vol 19 (10) ◽

pp. 1823-1836 ◽

Author(s):

Zhuo Feng ◽

Zhiyu Zeng ◽

Peng Li

Keyword(s):

Network Analysis ◽

Power Distribution ◽

Distribution Network ◽

Power Distribution Network ◽

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Fast transient analysis of 3-D stacked on-chip power distribution network with power/ground through silicon vias by using block latency insertion method

2013 IEEE Electrical Design of Advanced Packaging Systems Symposium (EDAPS) ◽

10.1109/edaps.2013.6724390 ◽

2013 ◽

Author(s):

Daisei Nagata ◽

Tadatoshi Sekine ◽

Hideki Asai

Keyword(s):

Power Distribution ◽

Transient Analysis ◽

Distribution Network ◽

Power Distribution Network ◽

Through Silicon Vias ◽

Insertion Method ◽

Latency Insertion ◽

Fast Transient ◽

On Chip ◽

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