MOSFET-like Carbon nanotube Field Effect Transistor based Full adder design

Author(s):  
Bappy Chandra Devnath ◽  
Satyendra N. Biswas
2019 ◽  
Vol 14 (11) ◽  
pp. 1512-1522 ◽  
Author(s):  
Seyedehsomayeh Hatefinasab

Scaling down the size of transistor in the nanoscale reduces the power supply voltage, as a result, the design of high-performance nano-circuit at low voltage has been considered. Most of digital circuits are composed of different components which determine the performance of the entire digital circuits. With the improvement of these components, the digital circuits can be optimized. One of these components is full adder for which various structures have been proposed to improve its performance, among them the two novel full adder structures are based on Gate-Diffusion Input (GDI) structure and half-classical XOR/XNOR logic (SEMI XOR/XNOR) modules. In this paper, Carbon Nanotube Field Effect Transistor (CNTFET)-based low power full adders by using SEMI XOR logic style and GDI structure are presented. Due to the incomparable thermal and mechanical properties of the CNTFET, it can be the first alternative to substitute the metal oxide field effect transistors (MOSFET). The digital circuits have the better performance based on CNTFET. Therefore, the three proposed full adders in this paper are designed based on CNTFET technology with many merits, such as low power dissipation, less energy delay product (EDP), and high speed at various supply voltages, frequencies, temperatures, load capacitors, and the number of tubes. Moreover, these proposed full adders occupy the minimum area consumption and have better performance in comparison with previous standard full adders. All simulations are done by using the Synopsys HSPICE simulator in 32 nm-CNTFET technology and layout of all full adder circuits are presented on Electric.


2021 ◽  
Author(s):  
Salomé Forel ◽  
Leandro Sacco ◽  
Alice Castan ◽  
Ileana Florea ◽  
Costel Sorin Cojocaru

We design a gas sensor by combining two SWCNT-FET devices in an inverter configuration enabling a better system miniaturization together with a reduction of power consumption and ease of data processing.


Sign in / Sign up

Export Citation Format

Share Document